Applications, development tools, FPGA, C, WEB
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Suggestions / ideas on how to accomplish my project?
1, 2 by mnordgard Mon Nov 27, 2017 2:48 pm
12 Replies
397 Views
by pavel
Fri Dec 01, 2017 8:38 am
Need example code of PID and FIR filter using verilog
by amin Sat Nov 25, 2017 6:05 am
3 Replies
140 Views
by amin
Mon Nov 27, 2017 11:25 am
My first FPGA design
by tsitsimp Thu Dec 15, 2016 2:11 pm
6 Replies
1933 Views
by amin
Mon Nov 27, 2017 7:28 am
scpi-server issues
by simone.mannori Sun Nov 26, 2017 8:39 am
0 Replies
51 Views
by simone.mannori
Sun Nov 26, 2017 8:39 am
FPGA Filter programming with Verilog
by TheWickedOne Mon Aug 31, 2015 11:11 am
9 Replies
4699 Views
by amin
Sat Nov 25, 2017 4:09 am
Generating a burst infinite times
by shonen3000 Fri Nov 24, 2017 5:52 pm
0 Replies
70 Views
by shonen3000
Fri Nov 24, 2017 5:52 pm
Signal generation via HDL Coder
1, 2 by rothmart Wed Oct 19, 2016 2:33 pm
12 Replies
3407 Views
by amin
Thu Nov 23, 2017 3:08 pm
What's the reason behind LCR meter frequencies limitations ?
by vladkrem Thu Nov 16, 2017 10:45 pm
0 Replies
94 Views
by vladkrem
Thu Nov 16, 2017 10:45 pm
Interface between C/C++ code created by Xcos (Scilab) and RP
by JackTheRippchen Thu Nov 16, 2017 10:52 am
0 Replies
96 Views
by JackTheRippchen
Thu Nov 16, 2017 10:52 am
Vivado question for buffered data acquisition slow ADCs
by vhd Tue Nov 14, 2017 4:25 pm
0 Replies
95 Views
by vhd
Tue Nov 14, 2017 4:25 pm
GRC Windows/Ubuntu gr-fosphor + rp transciever
by Ste_Trat Fri Nov 10, 2017 6:43 pm
2 Replies
148 Views
by Ste_Trat
Sat Nov 11, 2017 10:10 pm
Changing the number of samples obtained
by vaishsuri Thu Nov 09, 2017 1:38 pm
1 Replies
145 Views
by JohnnyMalaria
Thu Nov 09, 2017 9:38 pm
Errno 32 Broken Pipe
by benbaltes Tue Sep 13, 2016 12:18 am
4 Replies
1044 Views
by Matija
Thu Nov 09, 2017 4:05 pm
Access DMA register
by jporte Mon Nov 06, 2017 5:59 pm
0 Replies
127 Views
by jporte
Mon Nov 06, 2017 5:59 pm
Scope trouble
by HD13 Mon Oct 16, 2017 6:18 pm
5 Replies
448 Views
by HD13
Thu Nov 02, 2017 7:33 pm
MyFirstApp example : does not work
by hvanmunster@gmail.com Mon Oct 23, 2017 10:01 pm
2 Replies
236 Views
by JackTheRippchen
Thu Nov 02, 2017 2:38 pm
New User: Setting Up the Software
by mishra.kanhaiya91 Sat Sep 23, 2017 9:18 pm
3 Replies
393 Views
by amike88
Thu Nov 02, 2017 11:35 am
/opt/redpitaya/www/apps/ - read-only file system
by JackTheRippchen Wed Nov 01, 2017 11:48 am
2 Replies
182 Views
by JackTheRippchen
Wed Nov 01, 2017 4:48 pm
LCR Meter information
by mnordgard Wed Sep 06, 2017 1:50 pm
1 Replies
232 Views
by Mennem
Mon Oct 30, 2017 5:01 pm
Segmentation fault after making librp.so
by Matija Mon Apr 10, 2017 3:40 pm
3 Replies
539 Views
by mishra.kanhaiya91
Mon Oct 30, 2017 4:24 pm
Developing using Eclipse IDE on Windows
by Črt Valentinčič Mon Jul 14, 2014 12:21 pm
8 Replies
4630 Views
by ruben.valderas
Fri Oct 27, 2017 11:11 pm
PowerSDR (OpenHPSDR) vs. HDSDR
by Drachenfrucht Tue Oct 10, 2017 10:07 pm
1 Replies
259 Views
by Drachenfrucht
Fri Oct 27, 2017 7:07 pm
PID Integrator Hold
1, 2, 3 by ClaireE47 Sat Oct 25, 2014 1:38 am
27 Replies
12996 Views
by amin
Tue Oct 24, 2017 5:16 am
FPGA bit vs bin file
by makkie2002 Wed Mar 04, 2015 11:10 pm
9 Replies
2595 Views
by pavel
Sun Oct 22, 2017 1:34 pm
Problems rebuilding Pavel's LED Blinker
by JPCoetzee1 Fri Oct 20, 2017 10:11 am
4 Replies
216 Views
by JPCoetzee1
Sat Oct 21, 2017 9:10 am

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