Larger capture buffer and clock sync between RPs
Posted: Sun Aug 13, 2017 8:24 pm
1. Please increase the buffer size significantly from 16K to, say, 1M and/or provide two buffers to allow continuous capture by double buffering.
2. Implement synchronization between RPs. It is possible and has been demonstrated very admirably by Koheron using SATA cables to daisy-chain 4 RPs but it requires a different SD image and steep learning curves (Linux, Vivado, Verilog, FGPA etc etc). This ability is implied by STEMlab but not implemented. Please provide a simple way to switch between internal and external reference clocks. Always supply the actual reference clock via SATA cable to the next RP. Provide a SCPI function to simply select the source. e.g, CLK:INT or CLK:EXT.
The lack of both of these are causing me a lot of frustration and taking a lot of my time to work around. Implementing them would solve all my issues.
I'm sure plenty of other RP owners would support at least one of these requests.
Thanks.
2. Implement synchronization between RPs. It is possible and has been demonstrated very admirably by Koheron using SATA cables to daisy-chain 4 RPs but it requires a different SD image and steep learning curves (Linux, Vivado, Verilog, FGPA etc etc). This ability is implied by STEMlab but not implemented. Please provide a simple way to switch between internal and external reference clocks. Always supply the actual reference clock via SATA cable to the next RP. Provide a SCPI function to simply select the source. e.g, CLK:INT or CLK:EXT.
The lack of both of these are causing me a lot of frustration and taking a lot of my time to work around. Implementing them would solve all my issues.
I'm sure plenty of other RP owners would support at least one of these requests.
Thanks.