FPGA Lesson 6 “Moving Average”

[jwo251]

Hi all,

I am new to the Red Pitaya trying to get the simple moving average tutorial working on my 125-14 board. The simulation runs in Vivado as expected but does not look like the tutorial after uploading the bitstream to the RP, changing the address in the fpga.conf file, and booting up Scopegenpro from the web app. I am concerned that IN2 looks like noise, but it still seems to be getting filtered. Are there any known issues that would make the IN2 signal not match the OUT1 signal after connection here? When testing with the default oscope bitstream, OUT1 and IN2 do match.

Oscope display before running monitor 0x40600008 3:


Oscope display after running monitor 0x40600008 3:


Edit: I hooked the RP up to an external oscope and signal gen, and the problem seems to be that OUT1 is actually outputting no signal despite what the scopegenpro app displays. When I connect IN2 to an external signal, it works properly. Now I need to figure out what is preventing OUT1 from outputting its signal despite it appearing to do so on the web application.

[redpitaya]

Hello jwo251,

Sorry for the late reply.

You can find the tutorial in English here:
https://lniv.fe.uni-lj.si/redpitaya/redpitaya-proc.htm

If you did not connect the IN and OUT channels with the SMA cable, it is possible that you need to turn on the Loopback feature:

Code: Select all

monitor 0x40301000
monitor 0x4000000c 1

It is possible that some setting inside the reprogrammed FPGA is interfering with the OUT1 (for example if one of the dat_a_o or dat_b_o signals is connected to 0), which would prevent the oscilloscope from operating properly.

Please note that the output signal that is displayed in the oscilloscope application is just for reference (how the signal should look and not how it actually does). It is possible that the signal is displayed in the oscilloscope, but the signal is not actually generated (i.e. when the output is not turned ON). So if there are two conflicting instructions (in the oscilloscope and inside FPGA), it is possible that the signal will not be present at the output.

[redpitaya]

Otherwise the tutorials provided by the University of Ljubljana, LNIV laboratory are a great way to learn the interaction between C programs and FPGA.

https://lniv.fe.uni-lj.si/redpitaya/