Preset configuration of Proc System IP core for Red Pitaya

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carlos.e.teixeira
Posts: 23
Joined: Mon Nov 28, 2016 1:00 pm

Preset configuration of Proc System IP core for Red Pitaya

Post by carlos.e.teixeira » Fri Dec 09, 2016 12:14 pm

Hi everyone!

In this tutorial, it is possible to download the preset configuration (through a .tcl file) of the processing system IP core for Zybo board (See Figure 21).

I would like to know if anybody has a .tcl file containing these preset configurations for of the processing system IP core for the Red Pitaya.

I know Zybo board and Red Pitaya board are based on the same Zynq device, which is xc7z010clg400-1. However, I suppose that, as we have different on-board peripherals (comparing both Zynq-based boards), the .tcl file of the processing system IP would be different as well.

Am I correct?

Thanks in advance!

Regards!

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Preset configuration of Proc System IP core for Red Pita

Post by Nils Roos » Fri Dec 09, 2016 12:47 pm

The configuration you are looking for is included in the /fpga/prj/*/ip/system.tcl script of each project. (for example /fpga/prj/classic/ip/system.tcl)

Look for these lines:

Code: Select all

  # Create instance: processing_system7, and set properties
  set processing_system7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7 ]
  set_property -dict [ list \

carlos.e.teixeira
Posts: 23
Joined: Mon Nov 28, 2016 1:00 pm

Re: Preset configuration of Proc System IP core for Red Pita

Post by carlos.e.teixeira » Fri Dec 09, 2016 1:23 pm

Thank you so much!

pavel
Posts: 789
Joined: Sat May 23, 2015 5:22 pm

Re: Preset configuration of Proc System IP core for Red Pita

Post by pavel » Fri Dec 09, 2016 2:53 pm

I think that the exact equivalent of the file under question is this one:
https://github.com/Koheron/koheron-sdk/ ... preset.tcl

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Preset configuration of Proc System IP core for Red Pita

Post by Nils Roos » Fri Dec 09, 2016 4:19 pm

I think that the exact equivalent of the file under question is this one...
That file seems to be only a partial configuration, it's missing eg. the AXI settings. It's also setting different FPGA clock frequencies.

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