Hi everyone!
In this tutorial, it is possible to download the preset configuration (through a .tcl file) of the processing system IP core for Zybo board (See Figure 21).
I would like to know if anybody has a .tcl file containing these preset configurations for of the processing system IP core for the Red Pitaya.
I know Zybo board and Red Pitaya board are based on the same Zynq device, which is xc7z010clg400-1. However, I suppose that, as we have different on-board peripherals (comparing both Zynq-based boards), the .tcl file of the processing system IP would be different as well.
Am I correct?
Thanks in advance!
Regards!
Preset configuration of Proc System IP core for Red Pitaya
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Re: Preset configuration of Proc System IP core for Red Pita
The configuration you are looking for is included in the /fpga/prj/*/ip/system.tcl script of each project. (for example /fpga/prj/classic/ip/system.tcl)
Look for these lines:
Look for these lines:
Code: Select all
# Create instance: processing_system7, and set properties
set processing_system7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7 ]
set_property -dict [ list \
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Re: Preset configuration of Proc System IP core for Red Pita
Thank you so much!
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Re: Preset configuration of Proc System IP core for Red Pita
I think that the exact equivalent of the file under question is this one:
https://github.com/Koheron/koheron-sdk/ ... preset.tcl
https://github.com/Koheron/koheron-sdk/ ... preset.tcl
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Re: Preset configuration of Proc System IP core for Red Pita
That file seems to be only a partial configuration, it's missing eg. the AXI settings. It's also setting different FPGA clock frequencies.I think that the exact equivalent of the file under question is this one...
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