Applications, development tools, FPGA, C, WEB
#8186 by vhd
Tue Nov 14, 2017 4:25 pm
Hello I'm new to Redpitaya and Xilinx FPGA, and I would like to use the 2 fast AI channels and 4 slow ADCs channels .
There is no problem for fast AI part because only 300 kHz sampling is frequency required , on the other hand I can't reliably acquire the 4 slow ADCs channels with 100 Khz sampling rate since the data from slow ADCs are not buffered and the API for C developpement is not fast enough .
One solution possible will be : add a stream fifo after xADC then use iio driver to retrieve the data . I don't know if it's doable or not , but still worth a try ... :?:
Anyway I started the project and installed Vivado 2017.2 and tried to compile the V0.94 project without modify anything .
However I got timing failed :
https://imgur.com/sUyIf9O
I think it comes from clock contraint on the xdc file .
https://github.com/RedPitaya/RedPitaya/blob/master/fpga/sdc/red_pitaya.xdc
It seems like the following signals haven't been considered as clock :
dac_clk_o
dac_clk_2x
....

However they have been defined here :
https://github.com/RedPitaya/RedPitaya/blob/master/fpga/prj/v0.94/rtl/red_pitaya_top.sv
And I got also these warnings with RTL analysis.
[Vivado 12-627] No clocks matched 'dac_clk_o'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":214]
[Vivado 12-627] No clocks matched 'dac_clk_2x'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":215]
[Vivado 12-627] No clocks matched 'dac_clk_2p'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":216]
[Vivado 12-627] No clocks matched 'dac_clk_1x'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":218]
[Vivado 12-627] No clocks matched 'dac_clk_2x'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":219]
[Vivado 12-627] No clocks matched 'dac_clk_2p'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":220]
[Vivado 12-627] No clocks matched 'ser_clk'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":221]
[Vivado 12-627] No clocks matched 'pdm_clk'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":222]
[Vivado 12-627] No clocks matched 'dac_clk_o'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":223]
[Vivado 12-627] No clocks matched 'dac_clk_2x'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":223]
[Vivado 12-627] No clocks matched 'dac_clk_o'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":224]
[Vivado 12-627] No clocks matched 'dac_clk_2p'. ["C:/Users/pc/Desktop/v0.94/sdc/red_pitaya.xdc":224]

Probably something is missing .
In short my questions are how these signals can be defined as clock ? Any help to compile the project or idea about buffered data acquisition slow for ADCs is highly appreciated .
Thank for reading .

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