AXI bus

[Carlos]

Thanks Nils,

then I will use the conventional method (16k buffer).

[hokim]

Hi
I'm interested in direct ddr write from PL through AXI HP for high throughput.
axi_master.v was written for that.
I found some bug in axi_master.v while making vhdl version for my project.
axi_master.v has response error of DECERR(Decode error) due to wrong awcache and awprot values
awcache and awprot should be "0011" and "000" respectively.
My vhdl version works well after that modification.

This is patch for axi_master.v

Code: Select all

--- axi_master.v.orig   2016-02-18 11:34:04.819080439 +0900
+++ axi_master.v    2016-02-18 12:05:14.866771702 +0900
@@ -101,8 +101,8 @@
 assign axi_awid_o    = ID ;
 assign axi_awsize_o  = {2'b01,(DW==64)} ; // 4 or 8 byte transfer      ; // write burst size
 assign axi_awlock_o  = 2'h0   ; // normal
-assign axi_awcache_o = 4'h0   ; // non-cacheable
-assign axi_awprot_o  = 3'b010 ; // data, non-secured, unprivileged
+assign axi_awcache_o = 4'h3   ; // non-cacheable
+assign axi_awprot_o  = 3'b000 ; // data, non-secured, unprivileged

 reg [    4-1: 0] wr_cnt           ;
 reg [    4-1: 0] axi_awwr_pt      ;
@@ -291,8 +291,8 @@
 assign axi_arid_o    = ID ;
 assign axi_arsize_o  = {2'b01,(DW==64)} ; // 4 or 8 byte transfer
 assign axi_arlock_o  = 2'h0   ; // normal
-assign axi_arcache_o = 4'h0   ; // non-cacheable
-assign axi_arprot_o  = 3'b010 ; // data, non-secured, unprivileged
+assign axi_arcache_o = 4'h3   ; // non-cacheable
+assign axi_arprot_o  = 3'b000 ; // data, non-secured, unprivileged

 reg [4-1: 0] rd_cnt  ; // counts data received by system port
 reg          nxt_burst_rdy;

[Nils Roos]

Wow, great find. Thanks a lot !

[Carlos]

Hi, thanks for the info .
I don`t know the VHDL code or as an object file from the source is generated (I'm learning it ...) .
I suppose I should download the source code , modify , compile and generate the bit file to load it into the FPGA.
What compiler do you use?
Simply changing these values ​​work properly ?

Thank you.

[hokim]

Hi,
I have not yet tested it with red pitaya
I tested vhdl version of axi_master with zedboard and found that bug and the solution.
Please apply the patch file to red pitaya source code
(https://github.com/RedPitaya/RedPitaya/ ... i_master.v)
Then reproduce bit file.
I'm sure it will work well.

[Nils Roos]

I'm sure it will work well.

It does, indeed.

I suppose I should download the source code , modify , compile and generate the bit file to load it into the FPGA.

I've prepared the bitstream and a replacement boot.bin for you to use in case you have trouble building the whole thing.

[Carlos]

Hokim , Nils

Thank you!!! It works very well!!!
I owe you one.

Now learn VHDL. This card has no limits .

[janh]

There seems to be another bug. The AXI write pointer never points to any of the first 8 bytes of the buffer and sometimes points to the 8 bytes beyond the buffer. For example, if your buffer has a size of 0x01000000 bytes, the write pointer is always greater than or equal to BUFFER_ADDRESS+0x00000008 and less than or equal to BUFFER_ADDRESS+0x01000008. In order to test if samples get written beyond the buffer, I mapped 8 extra bytes without telling the scope. And indeed, there was sample data. I suspected that the position of the sample data was shifted by 8 bytes, so I looked at the first 8 bytes of the buffer. However, there was sample data too. The bug is probably in the axi_wr_fifo module, but I don't know where.

I made a program to demonstrate to the bug based on https://github.com/RedPitaya/RedPitaya/ ... /axi_adc.c. "./fifo_bug position" constantly reads the write pointer and prints the minimum and maximum values each second. "./fifo_bug content_start" prints the value of the first 8 bytes of the buffer each second and "./fifo_bug content_end" prints the value of the first 8 bytes beyond the buffer each second.

[Nils Roos]

A very interesting discovery! I haven't looked at the axi_wr_fifo very closely, I guess it's time I did that.
On the other hand, one of the Red Pitaya developers announced that they will be discontinuing the module in its current form (at an undisclosed point in the future).

Anyway, thanks for finding out and reporting!
Regards
Nils

[Carlos]

Hello Nils,

do you know if this is solved in version 0.97?

Thanks. Carlos.