AXI bus

[Carlos]

Hi, I am using the AXI bus to capture signals over 16K . Is there information about this method of capture ? Sample programs ?
Is it faster or slower than the conventional method ?

I've searched the forum but there is little information on the subject.

Thank you!!!

[Nils Roos]

Using the AXI HP bus to transfer samples out of the fpga via DMA is much faster than the conventional method. On top of that it is not limited to a 16k buffer.

There is not yet an official example, but I have recently put together some code that demostrates how to program the AXI HP transfer. You can find it in this branch of my RedPitaya fork, in Examples/C/axi_adc.c.

[Carlos]

Thanks Nils,

I've been testing the AXI bus but does not write anything in the DMA memory. Correctly updates the "CHX_AXI_write_pointer_trigger" and "CHX_AXI_write_pointer_current" pointers but samples writes in the buffer memory of 16K . Is it possible that the version of the FPGA is not correct ?

[Nils Roos]

If the 'AXI write pointer trigger' etc. registers are being updated, you have the correct version of the FPGA logic.
(with a wrong version, these registers would contain constant zero)

I'd need to see your code to tell you more.

[Carlos]

Thanks Nils!!!

I 'm going crazy with this problem.
I put the code ( I have removed what is not relevant )

Code: Select all

static const uint32_t OSC_BASE_ADDR=0x40100000;
static const int            OSC_BASE_SIZE=0xAC;

static const uint32_t DAT_BASE_ADDR=0x40110000;
static const int            DAT_BASE_SIZE=0xFFFF; 

static const uint32_t RAM_ADDRESS=0x1E000000;
static const uint32_t RAM_SIZE=0x01000000;

typedef struct
{
	uint32_t conf;
	uint32_t triggSource;
	uint32_t chAThreshold;
	uint32_t chBThreshold;
	uint32_t delayTrig;
	uint32_t dataDec;
	uint32_t wrPointCur;
	uint32_t wrPointTri;
	uint32_t chAHyst;
	uint32_t chBHyst;
	uint32_t avrDec;
	uint32_t preTrigCount;
	uint32_t chAEqFilAA;
	uint32_t chAEqFilBB;
	uint32_t chAEqFilKK;
	uint32_t chAEqFilPP;
	uint32_t chBEqFilAA;
	uint32_t chBEqFilBB;
	uint32_t chBEqFilKK;
	uint32_t chBEqFilPP;
	uint32_t chAAxiLowAdr;
	uint32_t chAAxiUpAdr;
	uint32_t chAAxiDelTri;
	uint32_t chAAxiEnMas;
	uint32_t chAAxiWrTri;
	uint32_t chAAxiWrCur;
	uint32_t reserved_0x68;
	uint32_t reserved_0x6C;
	uint32_t chBAxiLowAdr;
	uint32_t chBAxiUpAdr;
	uint32_t chBAxiDelTri;
	uint32_t chBAxiEnMas;
	uint32_t chBAxiWrTri;
	uint32_t chBAxiWrCur;
	uint32_t reserved_0x88;
	uint32_t reserved_0x8C;
	uint32_t trigDebTimer;
	uint32_t reserved_0x94;
	uint32_t reserved_0x98;
	uint32_t reserved_0x9c;
	uint32_t accDatSeqLen;
	uint32_t accDatOffChA;
	uint32_t accDatOffChB;
}Oscilloscope_st; 

struct conf_Bits
{
	uint32_t armTrigger:1;
	uint32_t resetStateMachine:1;
	uint32_t triggerStatusBef:1;
	uint32_t reserved:29;	
}

static Oscilloscope_st *osc_st;
static int16_t *ram_dma;

int fd=NULL;
if((fd=open("/dev/mem",O_RDWR|O_SYNC))==-1){return EXIT_FAILURE;}

osc_st=mmap(NULL,OSC_BASE_SIZE,PROT_READ|PROT_WRITE,MAP_SHARED,fd,OSC_BASE_ADDR);
ram_dma=mmap(NULL,RAM_SIZE,PROT_READ,MAP_SHARED,fd,RAM_ADDRESS);

uint32_t tmp;
tmp=osc_st->conf;
((struct conf_Bits *)(&tmp))->resetStateMachine=ON;
osc_st->conf=tmp;

osc_st->dataDec=1; 					//decimation

osc_st->chAAxiEnMas=ON;

osc_st->chAAxiLowAdr=RAM_ADDRESS;
osc_st->chAAxiUpAdr=RAM_ADDRESS+RAM_SIZE;

osc_st->delayTrig=30000;				//Num Samples
osc_st->chAAxiDelTri=30000;

tmp=osc_st->conf;
((struct conf_Bits *)(&tmp))->armTrigger=ON;		//Arm trigger
osc_st->conf=tmp;

osc_st->triggSource=1                                   			//Inmediate trigger;

do{}while(osc_st->triggSource!=0);

printf("done\n");
printf("%x - %x =  %x\n",osc_st->chAAxiWrTri,osc_st->chAAxiWrCur,osc_st->chAAxiWrCur-osc_st->chAAxiWrTri);
//this registers are correct.

int a;
for(a=20;a<200;a++){printf("%d  ",ram_dma[a]);}  	//all to 255. error

I tried it in different ecosystems and in all behave the same .

Thank you very much again.
Carlos.

[Nils Roos]

Hrm, I think we are going to have to face the possibility that the AXI code that is there is not fully doing what it is supposed to be doing.

When I try your code - and different variations of my own example code - I read seemingly random garbage, but oddly enough it's always mostly the same (not exactly though) garbage, even through power cycles. Can't fathom what that signifies.

If the logic is really broken, I'd rather add trigger capability to my own AXI recording design than try to debug this. I wrote in another thread that it is not easy to include triggering, and that's still true, but it's not terribly difficult, either.

[Carlos]

Thanks Nils.


when you say:

and different variations of my own example code

At what changes do you mean?.

I'll try "Ch A triggering" to see if it works well.

Thanks.

[Nils Roos]

I tried different trigger sources, single channel and dual channel recording and with or without intermediate cacheable buffers. The results were that nothing seems to actually be written into the DMA region in all cases.

[Carlos]

Nils, sorry but I do not understand . How should I do to use the AXI bus to read the ADC?

Your code works fine?

Thanks.

[Nils Roos]

Your code works fine?

No, it doesn't, that was my entire point.
The AXI recording logic was added without much announcement or software support about a year ago. Since it was committed by one of the original Red Pitaya developers, I assumed that it would work, but never tested it thoroughly; I only verified that it sets the write and trigger pointers correctly, but never examined the data - my bad.

However, I had developed my own version of a continuous recorder with AXI HP, and that works fine. It does not support triggering yet, though.