Vivado Workflow - Beginner Questions

Applications, development tools, FPGA, C, WEB
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lhochstetter
Posts: 55
Joined: Tue Mar 01, 2016 1:43 pm

Vivado Workflow - Beginner Questions

Post by lhochstetter » Mon May 30, 2016 3:51 pm

Hello everyone,

I'm fairly new to the entire FPGA development scene and have some issues understanding the basic workflow
when developing an application using the FPGA.

From what I've red Vivado is structured in three parts: HLS, "Vivado itself", SDK

Suppose I have an algorithm to add to vectors I'd like to implement in the FPGA:

I'd write the C Code in HLS and verify it using the test bench. Once this is done I'd import the generated .rtl files in "Vivado itself" / the Redpitaya project.
I'd then run Synthesis, Implementation and Bitstream Generation. The implemented hardware and bitstream are then exported to the SDK,
so I can write an application for the ARM using the implemented FPGA vector addition function.

Did I get the general ideas right?

Thanks

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Vivado Workflow - Beginner Questions

Post by Nils Roos » Tue May 31, 2016 10:38 pm

Full disclosure: I've never used HLS, I'm just extrapolating from the HLS tutorials and examples.

The first point to mention is:
If you plan to integrate your logic design with the existing Red Pitaya's functions, and want to keep the bazaar-apps, commandline tools, and linux OS (with all its infrastructure like network stack, filesystem, memory management, etc.), then the ARM side of things will have to be done very differently. The drivers generated by the HLS and the SDK will not help you there - they are geared towards bare-metal systems (ie no OS).
This is no fundamental problem, but you should know what to expect: more footwork and less turn-key solutions on the software side, if you don't want to drop the OS.

Assuming you want to stick with the present software environment, the process would look like this:
1. write your algorithms and verify them in the HLS framework
2. generate IP blocks from the rtl output
3. integrate your new IP into the Red Pitaya block design (tcl-based approach)
4. write program to communicate with your logic via memory mapped registers / DMA

As I said, I haven't tried that approach, so if anybody has actual experience, please correct me if I'm wrong.

lhochstetter
Posts: 55
Joined: Tue Mar 01, 2016 1:43 pm

Re: Vivado Workflow - Beginner Questions

Post by lhochstetter » Thu Jun 02, 2016 12:06 pm

Thanks, Nils!

I'll try to get it working and post my results here.

The ARM-side piece of software would also feature an interface with the nginx server / web apps,
if I wanted to create a web app to display results, right?

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Vivado Workflow - Beginner Questions

Post by Nils Roos » Fri Jun 03, 2016 12:35 pm

The ARM-side piece of software would also feature an interface with the nginx server / web apps,
if I wanted to create a web app to display results, right?
Yes. To make your functions available to a web-app, you would build your code into a shared object library that exports a handful of functions to the bazaar-plugin in the nginx server.

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