Xilinx has a lot of good tutorials, but I can't point you to anything specific. Look through the contents of DocNav, which you can install alongside Vivado. In the meantime, I can answer your questions and explain some basics - that might help you to pick avenues for further search.
All things you do in Verilog and in the block designs are assembled into circuits in the programmable logic (PL). In order for these circuits to do anything useful, they need interfaces with the device pins and/or on-chip peripherals. The latter include the ARM cores, DDR memory controller, UARTs, etc., and they are collectively called the processing system (PS).
"All these ports" in modules are the connections from one instance of a module to the code where the module is instantiated. The ports of the top module of a project (red_pitaya_top) are the interfaces where device pins can be assigned to. The assignment is done in the constraints (red_pitaya.xdc), where pins are connected to FPGA signals by way of the portname of the inputs/outputs of the top module.
A lot of the ports in red_pitaya_top belong to the PS ("FIXED_IO_*", "DDR_*"). Those are routed straight to the IP block instance that encapsulates the PS ("processing_system7" in the block design "system.bd"). If you follow the connections upwards (system.bd -> system_wrapper.v -> red_pitaya_ps.v -> red_pitaya_top.v), you'll notice that only some of the interfaces of processing_system7 connect to the top module ports. The remainder is where you can make a connection to the PS; this is mostly done in red_pitaya_ps for Verilog code or in the system.bd block design for IP blocks.
Connecting to the PS usually entails interfacing to an AXI bus. If you want registers in your logic to be mapped into the address space of the ARM cores, you implement an AXI slave that is connected to one of the PS's AXI masters. If you want your logic to control one of the on-chip peripherals, you implement an AXI master that connects to one of the PS's AXI slaves.
When you open the project in Vivado 2015.4, you are told that the project was created with an older version of Vivado. Choose to upgrade at that point. After the project opens, you are notified that some of the IPs are of an older version than is present in your Vivado. Select "Report IP status" and then upgrade with the button in the lower left of the report.
How can one convert a generated Bitstream to a bin file in Vivado 2015.4 (the program "promgen" is missing)?
You don't need to anymore. All recent versions of the xdevcfg device can process the *.bit files from Vivado directly.