it is me again with some questions about the ADC:
When I looked at the HW Schematics linked in the Wiki I noticed that the SPI Ports are connected to GND and in another thread it was mentioned that the ADC in fact is not configurable using SPI ... this applies to the RP v1.1, correct?
When I tried to figure out how you get measured data out of the ADC and found this piece of code in
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red_pitaya_top.v
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////////////////////////////////////////////////////////////////////////////////
// ADC IO
////////////////////////////////////////////////////////////////////////////////
// generating ADC clock is disabled
assign adc_clk_o = 2'b10;
//ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
//ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
// ADC clock duty cycle stabilizer is enabled
assign adc_cdcs_o = 1'b1 ;
// IO block registers should be used here
// lowest 2 bits reserved for 16bit ADC
always @(posedge adc_clk)
begin
adc_dat_a <= adc_dat_a_i[16-1:2];
adc_dat_b <= adc_dat_b_i[16-1:2];
end
// transform into 2's complement (negative slope)
assign adc_a = digital_loop ? dac_a : {adc_dat_a[14-1], ~adc_dat_a[14-2:0]};
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
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always @(posedge adc_clk)
begin
adc_dat_a <= adc_dat_a_i[16-1:2];
adc_dat_b <= adc_dat_b_i[16-1:2];
end
It also seems that the RP might support a 16bit ADC in the future considering the comments and the size of the array ...
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// transform into 2's complement (negative slope)
assign adc_a = digital_loop ? dac_a : {adc_dat_a[14-1], ~adc_dat_a[14-2:0]};
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
Reading some forum posts you seem to be limited to reading blocks of 16k values each (limits seem to be the resolution and sampling rate)... then again I skimmed bachelor thesis http://www.kip.uni-heidelberg.de/Veroef ... p/3265.pdf p.13 stating that (if I did my resarch properly) Nils did some modifications to the code to allow for longer data measurment ... is there a way to e.g. continously aquire data and store it in the RAM / SD Card or stream it using the Ethernet port / a WLAN dongle?
How the FPGA knows where the ADC is and which pins of the FPGA are used to communicate with the ADC is described in the HW schematics ... is this also stated in software at some point or are some of the FPGA pins simply hardwired to the ADC / DAC?
If I think up any new questions I'll post them here ...
Thanks in advance!