ADC - Interaction

[lhochstetter]

Hi everyone,

it is me again with some questions about the ADC:

When I looked at the HW Schematics linked in the Wiki I noticed that the SPI Ports are connected to GND and in another thread it was mentioned that the ADC in fact is not configurable using SPI ... this applies to the RP v1.1, correct?

When I tried to figure out how you get measured data out of the ADC and found this piece of code in

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red_pitaya_top.v

:

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////////////////////////////////////////////////////////////////////////////////
// ADC IO
////////////////////////////////////////////////////////////////////////////////

// generating ADC clock is disabled
assign adc_clk_o = 2'b10;
//ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
//ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));

// ADC clock duty cycle stabilizer is enabled
assign adc_cdcs_o = 1'b1 ;

// IO block registers should be used here
// lowest 2 bits reserved for 16bit ADC
always @(posedge adc_clk)
begin
  adc_dat_a <= adc_dat_a_i[16-1:2];
  adc_dat_b <= adc_dat_b_i[16-1:2];
end
    
// transform into 2's complement (negative slope)
assign adc_a = digital_loop ? dac_a : {adc_dat_a[14-1], ~adc_dat_a[14-2:0]};
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};

I do not understand VHDL / Verilog but I do guess that the

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always @(posedge adc_clk)
begin
  adc_dat_a <= adc_dat_a_i[16-1:2];
  adc_dat_b <= adc_dat_b_i[16-1:2];
end

part does read the ADC data into FPGA memory every clock cycle of the ADC connected clock. Did I guess correctly?

It also seems that the RP might support a 16bit ADC in the future considering the comments and the size of the array ...

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// transform into 2's complement (negative slope)
assign adc_a = digital_loop ? dac_a : {adc_dat_a[14-1], ~adc_dat_a[14-2:0]};
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};

This part is particulary interessting ... I'd guess it allows you to create a connection between the DAC and ADC, which can be used in the Oscilloscope App where you can generate a signal an meassure the generated signal at the same time ... right?

Reading some forum posts you seem to be limited to reading blocks of 16k values each (limits seem to be the resolution and sampling rate)... then again I skimmed bachelor thesis http://www.kip.uni-heidelberg.de/Veroef ... p/3265.pdf p.13 stating that (if I did my resarch properly) Nils did some modifications to the code to allow for longer data measurment ... is there a way to e.g. continously aquire data and store it in the RAM / SD Card or stream it using the Ethernet port / a WLAN dongle?

How the FPGA knows where the ADC is and which pins of the FPGA are used to communicate with the ADC is described in the HW schematics ... is this also stated in software at some point or are some of the FPGA pins simply hardwired to the ADC / DAC?

If I think up any new questions I'll post them here ...

Thanks in advance!

[Nils Roos]

Hi again,

[...] part does read the ADC data into FPGA memory every clock cycle of the ADC connected clock. Did I guess correctly?

In a manner of speaking, yes. It reads the current ADC sample value into a one-sample sized input register, from where it is forwarded to all modules that process samples (currently, red_pitaya_scope and red_pitaya_pid).

This part is particulary interessting ... I'd guess it allows you to create a connection between the DAC and ADC, which can be used in the Oscilloscope App where you can generate a signal an meassure the generated signal at the same time ... right?

I believe the original intention of this feature was to facilitate the demo mode of the non-free apps, where you can only measure the output of the DAC in the oscilloscope. Since the digital datastream to the DAC is strictly deterministic, there's really no reasonable need for a digital loopback otherwise.

is there a way to e.g. continously aquire data and store it in the RAM / SD Card or stream it using the Ethernet port / a WLAN dongle?

That is what the project referred to in the paper is designed to do, actually.

[...] is this also stated in software at some point or are some of the FPGA pins simply hardwired to the ADC / DAC?

There is an explanation of how this is done in the first half of this post.

If I think up any new questions I'll post them here ...

Keep'em coming

Regards
Nils

[lhochstetter]

Thanks!

I'll re-read the linked sources tomorrow thoroughly and try to figure out how the measured data is passed ADC (->?) -> FPGA (->?) -> ARM ( -> ?) ...

[lhochstetter]

I read the linked posts and they were quite informative.

According to the first link I found the pin <-> port assignment in red_pitaya.xdc ...

My understanding is that each physical FPGA pin is assigned an unique ID to allow interaction by connecting it to a module's ports.

I'd guess that the used physical FPGA pins (connected to the above mentioned ports) are connected in hardware (as in soldered together) to the ADC pins ... otherwise I fail to understand how the FPGA interacts with the ADC on the physical level.

On to the ADC (->?) -> FPGA (->?) -> ARM ( -> ?) part:

I understand the ADC -> FPGA part (see above).

FPGA -> ARM is done by the memory mapped FPGA register etc.

The ARM then can send the data using the Ethernet port etc.

An alternative would be Nils' project allowing a more direct route from the ADC to the RAM ... (sounds quite impressive but I didn't played with it yet)

[Nils Roos]

My understanding is that each physical FPGA pin is assigned an unique ID to allow interaction by connecting it to a module's ports.
I'd guess that the used physical FPGA pins (connected to the above mentioned ports) are connected in hardware (as in soldered together) to the ADC pins ... otherwise I fail to understand how the FPGA interacts with the ADC on the physical level.

Correct, the physical pins are arranged in a grid (the form of package that the ZYNQ has is called a ball grid array - BGA) and each pin is designated with a letter and a number for row and column. The physical pins are soldered to traces on the printed circuit board which connect to the pins of other parts like the ADC.