Debug FPGA functionality

Applications, development tools, FPGA, C, WEB
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schaeds
Posts: 10
Joined: Thu Mar 03, 2016 10:22 am

Debug FPGA functionality

Post by schaeds » Tue Jun 21, 2016 9:02 am

Dear all

I am trying to add some additional FPGA functionality to the design.. Unfortunately, it's not working as intended in the first shot.
Development approach:
1.) open existing Red Pitaya Design in Vivado
2.) adding additional functionality to the design
3.) running synthesis and implementation
4.) Download bit or bin file to the red pitaya --> /dev/xdevcfg

Is there a possibility during runtime for in-system-logic debuging of the fpga design? Or a similar functionality which could help to identify failures in the design? Reading registers, signal etc.?
The apporach above is kind of "blind" and try-and-error...

Thanks and kind regards
Stefan

schaeds
Posts: 10
Joined: Thu Mar 03, 2016 10:22 am

Re: Debug FPGA functionality

Post by schaeds » Tue Jun 21, 2016 9:13 am

Additional note: In the Elektor magazine's Red Pitaya article, is a comment about fpga debuging - but it's not shown, how does it work...
https://www.elektormagazine.com/assets/ ... 120381.pdf
It is also helpful that FPGA register contents and signal samples can be viewed as variables in ARM processor memory. This enormously simplifies debugging because you can peek into the FPGA while it is running.
--> What is this article talking about? Just the "normal" memory map functionality or additional debuging capability?

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Debug FPGA functionality

Post by Nils Roos » Tue Jun 21, 2016 10:37 am

Hi Stefan,

I think he was referring to the ability to read internal registers through the memory mapped AXI GP0 connection - which can be a big help if you don't happen to have problems with addressing or connecting memory mapped registers, or overall system stability.

Debugging logic designs is usually done during designtime with a simulator, and later in the running system with the help of the JTAG interface.
To use the simulator - which is part of Vivado - you write a testbench that acts as a host for the module you want to test. The testbench's purpose is to provide a planned sequence of input patterns to your module, and the simulator allows you to observe all internal signals in reaction to that input. I believe the Red Pitaya project already contains testbenches for the existing modules - though I haven't tried them.

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