Verilog example of fast ADC reading with the FPGA

[liorgolgher]

Hi Nils,

As detailed in our previous correspondence, we would like to program the FPGA of Red Pitaya to read the ADC and transmit the readings as quickly as possible to its GPIO pins. We have bought three Pitayas and contacted some experienced FPGA engineers, but still struggle to understand how to address the ADC through programmable logic.

Can you please direct us at a Verilog example of fast ADC reading with the FPGA?

Thanks,
Lior

[Nils Roos]

Hi Lior,

my suggestion would be to take the existing Red Pitaya logic design as both example and template, and adapt it to your needs.

There is not much you need to actively do to read the ADC, its output and clock is fed to a group of input buffers and is available to the programmable logic at all times. The adc_a and adc_b busses in red_pitaya_top.v carry the raw sample data in two's complement representation, clocked with adc_clk.

The GPIOs are driven by the IOBUF groups i_iobufp and i_iobufn in the same module.