Problems building the FPGA stream using Vivado 2016.2

[pefu]

I'm using a clone of the github repository.
I've followed the instructions given in https://github.com/RedPitaya/RedPitaya/ ... ld-process
However I got the following error messages:

Code: Select all

ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axis_clock_converter_i1 S_AXIS(system_S_AXI_STR_RX1_aclk) and /S_AXI_STR_RX1(system_S_AXI_STR_RX2_aclk)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /M_AXI_STR_TX1(system_M_AXI_STR_TX1_aclk1) and /axis_clock_converter_o1/M_AXIS(system_M_AXI_STR_TX1_aclk)
ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/pf/RedPitaya/fpga/prj/logic/project/redpitaya.srcs/sources_1/bd/system/system.bd 
...
ERROR: [Common 17-39] 'generate_target' failed due to earlier errors.
update_compile_order -fileset sources_1

What should I read to figure out what's wrong here?

[Nils Roos]

I guess you specified "PRJ=logic" for make, or didn't specify any PRJ in which case "logic" is the default.
It seems that the project "logic" is in development and can't be built at the moment. Depending on which bitstream you wanted to build, specify either "PRJ=logic_orig" (version with logic analyzer) or "PRJ=classic" (0.94).

If you did not previously build the devicetree, the make in "fpga" will fail at that step, because the devicetree repository is missing. But the bitstream has already been generated at that point and is fit for use.

[pefu]

Nils: That hint had helped me a lot. Thank you very much.