Signal generation via HDL Coder

Applications, development tools, FPGA, C, WEB
Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Signal generation via HDL Coder

Post by Nils Roos » Sat Nov 05, 2016 11:21 pm

DSP utilization of 100% warrants a closer look, I'd say. Were there any other warnings during implementation or DRC that stuck out? Perhaps you could pack up the project for me to look for myself?
i set up the input on idle
What did you do?
All in a day's work for Bicycle Repair Man

rothmart
Posts: 14
Joined: Fri Nov 13, 2015 3:10 pm

Re: Signal generation via HDL Coder

Post by rothmart » Mon Nov 07, 2016 11:46 am

Although this utilization i didn't noticed errors or critical warnings anyway. I didn't connect the input, so it was in open loop and shouldn't give any output - but it was high as you can see.

Maybe it is much easier, so i packed up the project to GitHub: https://github.com/tudoma/FIR_Filter/

amin
Posts: 53
Joined: Mon Feb 06, 2017 12:31 pm

Re: Signal generation via HDL Coder

Post by amin » Thu Nov 23, 2017 3:08 pm

Hi Rothmart,

I already edit your code https://github.com/tudoma/FIR_Filter/

I tried to make Sinus.v using your code as shown below:

Code: Select all

// -------------------------------------------------------------
// ...
// -------------------------------------------------------------

`timescale 1 ns / 1 ns

module Sinus
          (
           clk,
           reset,
           clk_enable,
           ce_out,
           Out1
          );


  input   clk;
  input   reset;
  input   clk_enable;
  output  ce_out;
  output  signed [13:0] Out1;  // sfix14


  wire enb;
  reg signed [13:0] Sine_Wave_out1;  // sfix14
  reg [4:0] address_cnt;  // ufix5


  assign enb = clk_enable;

// ADDRESS COUNTER
  always @ (posedge clk or posedge reset)
    begin: Sine_Wave_addrcnt_temp_process1
      if (reset == 1'b1) begin
        address_cnt <= 5'b00000;
      end
      else begin
        if (enb == 1'b1) begin
          if (address_cnt == 5'b11000) begin
            address_cnt <= 5'b00000;
          end
          else begin
            address_cnt <= address_cnt + 1;
          end
        end
      end
    end // Sine_Wave_addrcnt_temp_process1

// FULL WAVE LOOKUP TABLE
  always @(address_cnt)
  begin
    case(address_cnt)
      5'b00000 : Sine_Wave_out1 = 14'b00000000000000;
      5'b00001 : Sine_Wave_out1 = 14'b00000111110001;
      5'b00010 : Sine_Wave_out1 = 14'b00001111000100;
      5'b00011 : Sine_Wave_out1 = 14'b00010101011001;
      5'b00100 : Sine_Wave_out1 = 14'b00011010011001;
      5'b00101 : Sine_Wave_out1 = 14'b00011101101110;
      5'b00110 : Sine_Wave_out1 = 14'b00011111001100;
      5'b00111 : Sine_Wave_out1 = 14'b00011110101101;
      5'b01000 : Sine_Wave_out1 = 14'b00011100010010;
      5'b01001 : Sine_Wave_out1 = 14'b00011000000101;
      5'b01010 : Sine_Wave_out1 = 14'b00010010011000;
      5'b01011 : Sine_Wave_out1 = 14'b00001011100000;
      5'b01100 : Sine_Wave_out1 = 14'b00000011111011;
      5'b01101 : Sine_Wave_out1 = 14'b11111100000101;
      5'b01110 : Sine_Wave_out1 = 14'b11110100100000;
      5'b01111 : Sine_Wave_out1 = 14'b11101101101000;
      5'b10000 : Sine_Wave_out1 = 14'b11100111111011;
      5'b10001 : Sine_Wave_out1 = 14'b11100011101110;
      5'b10010 : Sine_Wave_out1 = 14'b11100001010011;
      5'b10011 : Sine_Wave_out1 = 14'b11100000110100;
      5'b10100 : Sine_Wave_out1 = 14'b11100010010010;
      5'b10101 : Sine_Wave_out1 = 14'b11100101100111;
      5'b10110 : Sine_Wave_out1 = 14'b11101010100111;
      5'b10111 : Sine_Wave_out1 = 14'b11110000111100;
      5'b11000 : Sine_Wave_out1 = 14'b11111000001111;
      default : Sine_Wave_out1 = 14'b11111000001111;
    endcase
  end


  assign Out1 = Sine_Wave_out1;

  assign ce_out = clk_enable;

endmodule  // gm_Sinus

i change header of "module gm_Sinus" with "module Sinus".
I call "module Sinus" to redpitaya_top.v like this code below:

Code: Select all

Sinus 
          (
           .clk(adc_clk),
           .reset(reset),
           .clk_enable(1'b1),
           .ce_out(ce_out),
           .Out1(data_dac_a)     //connected to   .dac_dat_a_i        (  data_dac_a       ),
          );
I already delete FIR_filter.v and filter.v and i delete FIR_filter declaration in redpitaya_top.v.
Also, i check RTL Schematic that Sinus block is no problem. i can see the sinus block Sine_Wave_out1_i --> out1 connect to dac_dat_a_i as well.
After i generate bitstream, i got red_pitaya_top.bit and copy it on Redpitaya/tmp in eclipse.
I copy to my system using this code:

Code: Select all

scp red_pitaya_top.bit root@192.168.11.25:/tmp
and load it using this code:

Code: Select all

cat /tmp/red_pitaya_top.bit >/dev/xdevcfg

Finally, i got response waveform signal 5MHz in DAC1 as well.

But the problem is when i put your sinus.v into default code of verilog redpitaya that i get from this link:
http://blog.redpitaya.com/examples-new/ ... -tutorial/
Sine_wave_out1_i-->Out1 of Sinus block not connect to dac_dat_a_i[13:0].
from this problem, of course i cannot get response signal in DAC1.

Hope you can understand this problem.

Thanks in advance,
Amin

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