RedPitaya Support Package for Matlab HDL Coder

[rothmart]

Hi,

in the last three month i tried out some FPGA implementation (real-time modulated communication system). Therefor i used a Matlab Simulink model and generated some verilog code with HDL Coder and integrated that into a vivado project. Some easy examples as well as the transmitter and some parts of the receiver worked quite well. But sometimes there are high hardware utilizations and timing errors, especially for precise filters and complex parts of the model. So i checked out the timing report and found out, that there is a long chain of components which seems to be the result of unspecific code generation. In my theorie for example the DSP48E should only feed with 48-bit, but the code sometimes has registers with much more bits. So the other operation has to be outsourced, which is noticeable in higher utilization and a timing lag.

Now i want to specify and pretend the rules of code generation. In Matlab's 'HDL Workflow Advisor' you can choose the 'FPGA Turnkey' and create an own custom board. My goal is to respect the limit of redpitaya. In another post i read that it's possible to add the redpitaya to FPGA Board Manager from red_pitaya.xml file, is that right? But when i choose this configuration file there are 'errors in loading board file'. Can you help me to modify that file or to create an own custom board?

Regards!

[pavel]

Have you tried to follow the instructions from this link?

red_pitaya.xml from my repository is equivalent to ZYBO_zynq_def.xml from the instructions.

[rothmart]

Isn't that a thing to connect an created IP-Core? Maybe i missunderstood the target workflow, but i think with 'FPGA Turnkey' the generated code should be balanced with the redpitaya's hardware. But for that option it's needed to create an custom board in Matlab HDL Workflow Advisor. My goal is to create therewith a specific code that has no timing lags. In this fpga board manager you can insert an .xml file, is that the same as red_pitaya.xml?

[pavel]

In this fpga board manager you can insert an .xml file, is that the same as red_pitaya.xml?

No, red_pitaya.xml is a ZYNQ definition file, not a board definition file.

A board definition file can be found at this link but according to this post this file has some bugs.

I don't think that a board definition file would help Matlab HDL to create a design that fits into the available resources. Defining the correct device (xc7z010) should be enough. Even in Vivado it's very easy to create a design that requires more resources than there are available.

Looking at the Matlab HDL documentation, I'd say that the parameters that could help to address the timing issues are described at this link.