Difference between Decimation Factor and Sampling Rate?

Applications, development tools, FPGA, C, WEB
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benbaltes
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Joined: Mon Sep 12, 2016 9:38 pm

Difference between Decimation Factor and Sampling Rate?

Post by benbaltes » Wed Jan 11, 2017 9:06 pm

Do these correspond to the same thing? I can't find any documentation detailing the two, but in examples they seem almost interchangable.

Nils Roos
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Location: Königswinter

Re: Difference between Decimation Factor and Sampling Rate?

Post by Nils Roos » Thu Jan 12, 2017 11:07 pm

Taken literally, the sampling rate of the Red Pitaya's ADC is always 125MSps per channel (as long as you use the on-board clock). The incoming samples optionally pass through an averager, which takes a number of samples (corresponding to the decimation factor) and writes the average of the whole lot into the output buffer. So the effective sampling rate at which samples are written into the output buffer for your retrieval is 125MSps / decimation.
Does that answer your question?

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