More Device Tree Questions

[xyefa]

I have a question ... while doing some device tree tinkering, I disabled UART1. When I recompiled the Linux kernel and booted up, the keyboard and mouse were no longer recognized/detected. I am guessing that I somehow interfered with these devices. What is the purpose of having 2 UARTS defined in the device tree? Can the Linux kernel make do with one?

How did this happen? UART1 uses pins on the E2 header that I wanted to use for something else. I figured it was just as easy to disable this UART. Another question related to this - Is there a way to re-map the UART1 pins on the E2 Header? Is there a pin controller node that can be defined to do this?

[jeanminet]

Hello,

You cannot do much with the 2 UART1 pins.
You could only use them for implementing a CAN bus protocol or for 2 GPIOs that you could access from Linux.

Best,
Jean

[Nils Roos]

I have a question ... while doing some device tree tinkering, I disabled UART1. When I recompiled the Linux kernel and booted up, the keyboard and mouse were no longer recognized/detected.

I have some counter-questions:
Did you only disable UART1 in the devicetree? (compare jeanminet's IP config)
What keyboard and mouse? (when asking things about a non-standard setup, assume that no one here knows about the setup you are running)

What is the purpose of having 2 UARTS defined in the device tree? Can the Linux kernel make do with one?

One UART handles the interface on E2, the other provides the kernel console that is available through the CON connector. The kernel itself does not need any UART, but if you want to use the CON console, you need the UART that handles it.

UART1 uses pins on the E2 header that I wanted to use for something else. I figured it was just as easy to disable this UART.

Disabling it in the devicetree is not enough, the physical device is connected to the pins as long as it is active in the ZYNQ IP configuration.

Another question related to this - Is there a way to re-map the UART1 pins on the E2 Header? Is there a pin controller node that can be defined to do this?

There is no output multiplexer which is reconfigurable at runtime - which you would need to use a "pin controller" device.

You could map the UART1 signals to the slow analog outputs. To do that, you would define them as EMIO. This would lead to some additional connections appearing on the ZYNQ IP block. You would route those to red_pitaya_top and replace the connections for the PWM DAC with them, and adapt the constraints to match.
Obviously, this is a FPGA redesign and thus to be considered static from the point of view of the devicetree.