AWG Trigger delayed

[tknopp]

I try to get synchronized fast input/output and if I got it right this can be accomplished using the AWG_PE trigger. However, I observe that when I use a trigger delay of 8192 which puts my signal to the beginning I still have about 25 samples delay (at decimation 1). Is that expected? I can now shift the signal by those samples but just wanted to know if I do the right thing.

This forum is by the way pretty helpful. I am using SCPI and the documentation is in parts wrong making it hard to get something working.

[Nils Roos]

ADC and DAC add a certain pipelining and conversion latency outside of the FPGA, and then there is a bit of internal pipelining and buffer latency on the signal busses as well. I detailled the contributions some time ago in another topic, but I can't find it right now. 25 samples (~200ns) does not seem too high for the complete round-trip.

This forum is by the way pretty helpful. I am using SCPI and the documentation is in parts wrong making it hard to get something working.

Thanks. The docs and the api have both been getting better though.
edit: by the way, I hope you know about the new scpi docs.

[tknopp]

Thanks.

Regarding the SCPI documentation. No, did not see that one. But still "ACQ:GET:DATA:FORMAT FLOAT" is wrong.
I just understood that the binary version comes with a small header that has to be read before the data comes. Actually, reading the scpi-server code can be very helpful

Cheers,

Tobias