cs-gpios - using a GPIO as a chip select?

[xyefa]

In the SPI documentation, it allows for the use of a GPIO as a Chip Select. This is the "cs-gpios" property. Is this possible on the Red Pitaya?

I have repurposed UART1 as a GPIO and I would like to use one pin as a Chip Select. I am interested in using GPIO-based SPI chip selects making the pins thatI took from from UART1 to communicate with an SPI-enabled peripherals as a CS1 (Chip Select/Slave Select 1). Does the Xilinx SPI driver support using a GPIO as a chip select?

cs-gpios is documented here: https://www.kernel.org/doc/Documentatio ... pi-bus.txt

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[Nils Roos]

I don't know whether the Xilinx spi driver supports that or not - I'd guess not - but you do not need to, anyway. Instead, you can rewire the SPI1 interface inside the FPGA and use the spi driver in it's standard way. On the FPGA-side, you'd have to

• reconfigure the ZYNQ-IP to map SPI1 to EMIO
• enable one or two additional SlaveSelects on SPI1
• disable UART1
• route the new SPI1 connections on the IP to red_pitaya_top and tie them to FIXED_IO_mio[8-12] - that's where UART1 and SPI1 were previously
• make sure that the external drivers for the MIO pins are configured correctly - since the devices on them are now disabled, they will no longer automatically inherit their configuration

Lastly, increase the number of selects for spi1 in the devicetree. That ought to do it.

[xyefa]

I don't know whether the Xilinx spi driver supports that or not - I'd guess not - but you do not need to, anyway. Instead, you can rewire the SPI1 interface inside the FPGA and use the spi driver in it's standard way. On the FPGA-side, you'd have to

1. Reconfigure the ZYNQ-IP to map SPI1 to EMIO
2. Enable one or two additional SlaveSelects on SPI1
3. Disable UART1
4. Route the new SPI1 connections on the IP to red_pitaya_top and tie them to FIXED_IO_mio[8-12] - that's where UART1 and SPI1 were previously
5. Make sure that the external drivers for the MIO pins are configured correctly - since the devices on them are now disabled, they will no longer automatically inherit their configuration

Lastly, increase the number of selects for spi1 in the devicetree. That ought to do it.

Thank you for the reply. I have done steps 1-3. I have some questions about step 4. The SPI port is on the IP, so I made it an external connection called (SP1_1).

I am not really sure which project file to make the necessary assignment. Do I need to EDIT the red_pitaya_top.v file and make the assignment to FIXED_IO_mio[8-12]? Or do I edit the system_processing_system7_0 and assign EACH SPI signal individually?

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[Nils Roos]

First, a small correction: SPI1's SS[0] is on FIXED_IO_mio[13], so it should be [8-13] instead of [8-12] in the above post.

It doesn't really matter where you inject the SPI1_1 signals into the FIXED_IO_mio bus, the important part is that the FIXED_IO_mio[8-13] signals from the red_pitaya_top module declaration are connected to the SPI1_1 signals from the ZYNQ IP (instead of their original connection to the FIXED_IO bus MIO[8-13] on the IP).

In any case, you have to take care that you connect the right signals from the 8-13 range:
8, 9 => SS[1,2]
10 => MOSI
11 => MISO
12 => SCLK
13 => SS[0]

[xyefa]

First, a small correction: SPI1's SS[0] is on FIXED_IO_mio[13], so it should be [8-13] instead of [8-12] in the above post.

It doesn't really matter where you inject the SPI1_1 signals into the FIXED_IO_mio bus, the important part is that the FIXED_IO_mio[8-13] signals from the red_pitaya_top module declaration are connected to the SPI1_1 signals from the ZYNQ IP (instead of their original connection to the FIXED_IO bus MIO[8-13] on the IP).

In any case, you have to take care that you connect the right signals from the 8-13 range:
8, 9 => SS[1,2]
10 => MOSI
11 => MISO
12 => SCLK
13 => SS[0]

Yes, I was wondering where I would make the connections - I will edit one of the Verilog files and make the assignments. Could this also be done by editing the Constraints File?

Thanks!

[xyefa]

Make sure that the external drivers for the MIO pins are configured correctly - since the devices on them are now disabled, they will no longer automatically inherit their configuration

Which drivers are your referring to? Are you referring to the Linux kernel drivers (in the kernel configuration)? Or are you referring to the pin attributes that are specified in Vivado?

[Nils Roos]

I was referring to the output driver circuits for the pins, whose properties (drive strength, slew rate, etc) you define in Vivado.

[xyefa]

I was referring to the output driver circuits for the pins, whose properties (drive strength, slew rate, etc) you define in Vivado.

Thank you for the clarification.

[xyefa]

I don't know whether the Xilinx spi driver supports that or not - I'd guess not - but you do not need to, anyway. Instead, you can rewire the SPI1 interface inside the FPGA and use the spi driver in it's standard way. On the FPGA-side, you'd have to

1. Reconfigure the ZYNQ-IP to map SPI1 to EMIO - Comment: I did this in the Block Design
2. Enable one or two additional SlaveSelects on SPI1 Comment: EMIO seems to enable all of them
3. Disable UART1 Comment: I did this in the Block Design
4. Route the new SPI1 connections on the IP to red_pitaya_top and tie them to FIXED_IO_mio[8-12] - that's where UART1 and SPI1 were previously Comment: I did this in the Verilog Wrapper file
5. Make sure that the external drivers for the MIO pins are configured correctly - since the devices on them are now disabled, they will no longer automatically inherit their configuration Comment: It looks like I need to do this in the CONSTRAINTS FILE. I may need to delete some old constraints related to the UART and enable some new ones.
6. Lastly, increase the number of selects for spi1 in the devicetree. That ought to do it. Comment: This is straightforward.

Hello Nils,

It looks like I need to (carefully) update the constraints file (.xdc) file. I could not set the EMIO driver properties in the GUI, so it looks like I need to set them in the constraints file as well as the delete the constraints related to UART1. I have been tinkering with this ... It looks like I am almost there.

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