FPGA RAM

[tzw]

Hey,
I'm trying to build a readable and writable RAM in the FPGA for storing a feedforward function. Synthesis works for the code, but when I test my code using the monitor tool I get the same value in all registers. I would really appreciate it, if someone more experienced could help me out . I tried to stick to the code which was written for the dac buffer in the scope module and the asg module

Here is a code snippet:

// discrete feedforward function
parameter FFRSZ = 14; //feedforward RAM Size 2^FFRSZ

reg [14-1:0] ram_ff_values[0:(1<<FFRSZ)-1]; //discrete feedforward function values
reg [14-1:0] ram_ff_slope[0:(1<<FFRSZ)-1]; //corresponding feedforward function slope for each value

//write to RAM
always @(posedge clk_i) begin
buf_value_we <= sys_wen && (sys_addr[19:16] == 'h1);
buf_slope_we <= sys_wen && (sys_addr[19:16] == 'h2);
ff_addr_w <= sys_addr[16-1:2];
end

always @(posedge clk_i) begin
if (buf_value_we) ram_ff_values[ff_addr_w] <= sys_wdata[14-1:0]; //write feedforward function values to RAM
end

always @(posedge clk_i) begin
if (buf_slope_we) ram_ff_slope[ff_addr_w] <= sys_wdata[14-1:0]; //write feedforward function slope values to RAM
end

//read buffer
always @(posedge clk_i) begin
ff_addr_r <= sys_addr[16-1:2];
ff_value_rd <= ram_ff_values[ff_addr_r];
ff_slope_rd <= ram_ff_slope[ff_addr_r];
end

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0 ;
sys_ack <= 1'b0 ;
end else begin
sys_err <= 1'b0 ;

casez (sys_addr[19:0])
20'h1zzzz : begin sys_ack <= sys_en; sys_rdata <= {{32-14{1'b0}}, ff_value_rd} ; end //read feedforward function values
20'h2zzzz : begin sys_ack <= sys_en; sys_rdata <= {{32-14{1'b0}}, ff_slope_rd} ; end //read feedforward function slope

default : begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase

end

[tzw]

Delaying the read enable like in the scope module fixed the problem.

always @(posedge clk_i) begin //delay read enable for RAM for 3 clock cycles
if (rstn_i == 1'b0)
rval <= 4'h0 ;
else
rval <= {rval[2:0], (sys_ren || sys_wen)};
end
assign rd_dv = rval[3];

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0 ;
sys_ack <= 1'b0 ;
end else begin
sys_err <= 1'b0 ;

casez (sys_addr[19:0])

20'h1???? : begin sys_ack <= rd_dv; sys_rdata <= {16'h0, 2'h0,ff_value_rd} ; end //read feedforward function values
20'h2???? : begin sys_ack <= rd_dv; sys_rdata <= {16'h0, 2'h0,ff_slope_rd} ; end //read feedforward function slope
default : begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase

end