triggering hold-off time

Applications, development tools, FPGA, C, WEB
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bittware
Posts: 3
Joined: Mon May 22, 2017 7:50 am

triggering hold-off time

Post by bittware » Tue May 23, 2017 1:23 pm

I read the other post that said the multiple triggering hold-off time is approx. 0.5ms.
I'd like to know what factor causes such limit. Should the buffer have to be filled out the RP is able to capture next triggering signal?
And does the decimation setting affect hold-off time?
Thanks for the help!

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