FPGA V0.94 Project Issues and Questions

Applications, development tools, FPGA, C, WEB
Post Reply
ayarema
Posts: 8
Joined: Sat Mar 25, 2017 1:35 am

FPGA V0.94 Project Issues and Questions

Post by ayarema » Sun Jun 04, 2017 11:08 pm

Currently i have a C program that monitors two input control lines and upon seeing a "record" state the C program sets up external trigger, decimation, and trigger delay. Another device creates the waveform. And the C program then sends 2k samples(SPI on RP has 4096 bytes transfer size limit for a single transmission) buffer out of the system via SPI to be processed by the PC. The C program uses the 0.94 bit stream for the API access.

The program has a few limitations, first is the fact that it can only send 2k samples at a time via SPI. And the second limitation is that transfer over SPI is around 2.5ms just for the data to go through the line at 21Mhz, ignoring all other things. For the application i am working on the critical part of the ADC is that it needs to be very low latency. So with a 8 bit parallel bus and the frequency around 50Mhz i should see a speed up of about 16x over the SPI speed. This would get me to around 156us per 2k of samples.

My goal is to do the following:
Take that same C program and implement it in FPGA fabric, so that there is a state machine that listens on these same control lines for a specific signal. Upon the signal it sets up CH1 to external trigger, sets decimation and trigger delay and starts acquiring. Then once the trigger is hit the FPGA code would then take the contents that are stored in the ADC buffer and send them out via an 8bit wide parallel interface to a Cypress USB 3.0 FX3 GPIF II interface. It would look something like this.
GPIF to FPGA.PNG
The program flow would be something like this:
-Control lines are set to indicate capture
-FPGA sets up the parameters for trigger and begins monitoring for trigger finish.
-Upon trigger finish the FPGA reads the fast ADC internal buffer at say 25Mhz, and sends out the High byte, then low byte on a 50Mhz clock.
-FPGA returns to monitoring the control lines

Here is what i have done currently:
Cloned the RedPitaya github repo and installed Vivado 2017.1 on Windows 10 Laptop.
Modified the red_pitaya_vavado.tcl script to only build the V0.94 project bitstream.
Rebuild the bitstream (To be tested for functionality with the C program). (tested failed)

Created a Ubuntu VM and installed Vivado 2017.1 on that. Was able to rebuild the v0.94 bitstream after recent repo updates. Tested the bitstream i get from build and it works on the RP. This tells me that my development environment is set up properly.

Here is where i am stuck
A)I found the red_pitaya_top.sv file in the V0.94 rtl directory. To me that seems like the best place to add this new module? I dont need the DAC, or the slow analog channels so a few things could be removed if there isnt enough space.
B) How do i set up the decimation, external trigger, trigger delay etc from the FPGA? And how do i begin capture and monitor the needed flags?
C) This would be done on the extension connector with the DIO_N and DIO_P pins. Do i need to do something to them to make sure they are driven just by that FPGA block and the software doesnt interfere? (external trigger would stay where it is) Note: the C program would go away and only bash script would be setup to load the 0.94 bit stream during boot.
D) Finally how do i read the internal buffer one 16bit int at a time and go through all 16k samples if needed?
You do not have the required permissions to view the files attached to this post.

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 23 guests