Differential clock input on LVCMOS18

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8lu3
Posts: 29
Joined: Thu Feb 25, 2016 7:05 pm

Differential clock input on LVCMOS18

Post by 8lu3 » Mon Oct 09, 2017 2:20 pm

Hi,
I want to use the clock-capable pins on the Sata connector S2 for an external differential input clock. All Sata pins are set to the single-ended IOSTANDARD LVCMOS18 in the redpitaya.xdc file by default and the clock capable pins are terminated with 100Ohms. Is there a IO primitive that generates a single-ended clock from the differential clock incoming on the single-ended Sata-pins (like ODDR can be used to create a diff. output clock on two single-ended LVCMOS pins) ?

thanks in advance

amike88
Posts: 78
Joined: Tue Mar 29, 2016 7:41 pm

Re: Differential clock input on LVCMOS18

Post by amike88 » Mon Oct 09, 2017 3:00 pm

Hi

what you are looking for is:
IBUFDS and IBUFGDS (from xilinx UG471)
The usage and rules corresponding to the differential primitives are similar to the
single-ended SelectIO primitives. Differential SelectIO primitives have two pins to and
from the device pads to show the P and N channel pins in a differential pair. N channel
pins have a B suffix. The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used
when an differential input buffer is used as a clock input.

8lu3
Posts: 29
Joined: Thu Feb 25, 2016 7:05 pm

Re: Differential clock input on LVCMOS18

Post by 8lu3 » Mon Oct 09, 2017 3:42 pm

Unfortunately, you can't use IBUFDS for single-ended LVCMOS pins. I tried this, but Vivado quits synthesis/implementation with a corresponding error.

amike88
Posts: 78
Joined: Tue Mar 29, 2016 7:41 pm

Re: Differential clock input on LVCMOS18

Post by amike88 » Mon Oct 09, 2017 5:34 pm

IBUFGDS is the primitive that is used to generate clocks from differential signals.
what you need to do is to change the IO standard to 1 of the supported diff standards, that also matches your requirements.
supported IO standards are:
  • LVDS
  • Mini_LVDS
  • RSDS
  • PPDS
  • BLVDS,
  • differential HSTL
  • differential SSTL
  • ...

8lu3
Posts: 29
Joined: Thu Feb 25, 2016 7:05 pm

Re: Differential clock input on LVCMOS18

Post by 8lu3 » Mon Oct 09, 2017 7:14 pm

Hmm, I'm not very familiar with this kind of electronics and so on and I'm a little confused by all this different logic families.
LVDS isnt available on the fpga bank. So, given the fact that the adcclk pins use diff_hstl I 18, this might be the way to go. But, on the other hand, the Sata connectors can be used to create a daisy chain of RedPitayas. So, shouldn't the iostandard be the same on input and output clock pins (but for the output pins it is recommended to use ODDRs and LVCMOS like it is done for the fpga_clk pins)?
I'm also a bit worried about changing all these iostandard. Don't you think the RedPitaya engineers chose them on purpose?

Btw, how do you drive diff_hstl. Could one just use a LVDS?

PS: Im referring to the schmetics from the docs and the fpga image v0.94

amike88
Posts: 78
Joined: Tue Mar 29, 2016 7:41 pm

Re: Differential clock input on LVCMOS18

Post by amike88 » Tue Oct 10, 2017 11:32 am

Yes you must match IO standards on both the receiving and transmitting side. (on both boards)

You should also take into account power supply of the particular bank.

For the output I recommend that you use:

Code: Select all

// OBUFDS: Differential Output Buffer
//         7 Series
// Xilinx HDL Language Template, version 2017.3

OBUFDS #(
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW")           // Specify the output slew rate
) OBUFDS_inst (
   .O(O),     // Diff_p output (connect directly to top-level port)
   .OB(OB),   // Diff_n output (connect directly to top-level port)
   .I(I)      // Buffer input
);

// End of OBUFDS_inst instantiation
This is the buffer you use, then you can choose any supported IOstandard.

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