Problems rebuilding Pavel's LED Blinker
Posted: Fri Oct 20, 2017 10:11 am
I can build Pavel's LED Blinker project and create a bootable SD card but I am having problems changing and RE-building it. I've made a small change to the LED blinking module red_pitaya_hk.v
I've commented out the line allowing the system to write to the LED register, to make sure that the only thing turning the LEDs on and off is the above code
Before re-running the build scripts I delete the red_pitaya_0_92/tmp directory to force a complete re-synthesis by Vivado. However, no matter what I do only LED[0] flashes at 1Hz i.e. exactly the same as the original build. Either Vivado is not re-synthesising red_pitaya_hk.v or the script is re-downloading the file from github, but I can't find that anywhere in the scripts.
I'm not an expert in Verilog (I am a VHDL engineer) but I understand the code.
Can anybody help? Many thanks
Code: Select all
// LED blinking
reg [ 8-1: 0] led_reg ;
reg [ 32-1: 0] led_cnt ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
led_reg[0] <= 1'b0 ;
led_reg[1] <= 1'b0 ;
led_reg[2] <= 1'b0 ;
led_reg[3] <= 1'b0 ;
led_reg[4] <= 1'b0 ;
led_reg[5] <= 1'b0 ;
led_reg[6] <= 1'b0 ;
led_reg[7] <= 1'b0 ;
led_cnt <= 32'h0 ;
end
else begin
led_reg[0] <= led_cnt[28] ;
led_reg[1] <= led_cnt[27] ;
led_reg[2] <= led_cnt[26] ;
led_reg[3] <= led_cnt[25] ;
led_reg[4] <= led_cnt[24] ;
led_reg[5] <= led_cnt[29] ;
led_reg[6] <= led_cnt[29] ;
led_reg[7] <= led_cnt[29] ;
led_cnt <= led_cnt + 32'h1 ;
end
end
Code: Select all
// if (sys_addr_i[19:0]==20'h30) led_reg[7:1] <= sys_wdata_i[8-1:1]
I'm not an expert in Verilog (I am a VHDL engineer) but I understand the code.
Can anybody help? Many thanks