Code: Select all
// LED blinking
reg [ 8-1: 0] led_reg ;
reg [ 32-1: 0] led_cnt ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
led_reg[0] <= 1'b0 ;
led_reg[1] <= 1'b0 ;
led_reg[2] <= 1'b0 ;
led_reg[3] <= 1'b0 ;
led_reg[4] <= 1'b0 ;
led_reg[5] <= 1'b0 ;
led_reg[6] <= 1'b0 ;
led_reg[7] <= 1'b0 ;
led_cnt <= 32'h0 ;
end
else begin
led_reg[0] <= led_cnt[28] ;
led_reg[1] <= led_cnt[27] ;
led_reg[2] <= led_cnt[26] ;
led_reg[3] <= led_cnt[25] ;
led_reg[4] <= led_cnt[24] ;
led_reg[5] <= led_cnt[29] ;
led_reg[6] <= led_cnt[29] ;
led_reg[7] <= led_cnt[29] ;
led_cnt <= led_cnt + 32'h1 ;
end
end
Code: Select all
// if (sys_addr_i[19:0]==20'h30) led_reg[7:1] <= sys_wdata_i[8-1:1]
I'm not an expert in Verilog (I am a VHDL engineer) but I understand the code.
Can anybody help? Many thanks