I'm FPGA beginner thus I started with an example from
by Zumy Topcagicred-pitaya-fpga-examples.readthedocs.io/en/latest/_downloads/StartprogrammingFPGAusingRedPitayaboard.pdf
It went smoothly up to point 10. Adding registers for our scaling factor.
During synthesis I got following errors:
ERROR: [Synth 8-448] named port connection 'custom_reg_0' does not exist for instance 'i_id' of module 'red_pitaya_id' [C:/Users1/Pawel/redpitaya_projects_2017_4/scope_custom_register/scope_custom_register.srcs/sources_1/imports/fpga/prj/classic/rtl/red_pitaya_top.sv:396]
ERROR: [Synth 8-448] named port connection 'custom_reg_1' does not exist for instance 'i_id' of module 'red_pitaya_id' [C:/Users1/Pawel/redpitaya_projects_2017_4/scope_custom_register/scope_custom_register.srcs/sources_1/imports/fpga/prj/classic/rtl/red_pitaya_top.sv:397]
ERROR: [Synth 8-448] named port connection 'custom_reg_2' does not exist for instance 'i_id' of module 'red_pitaya_id' [C:/Users1/Pawel/redpitaya_projects_2017_4/scope_custom_register/scope_custom_register.srcs/sources_1/imports/fpga/prj/classic/rtl/red_pitaya_top.sv:398]
ERROR: [Synth 8-448] named port connection 'custom_reg_3' does not exist for instance 'i_id' of module 'red_pitaya_id' [C:/Users1/Pawel/redpitaya_projects_2017_4/scope_custom_register/scope_custom_register.srcs/sources_1/imports/fpga/prj/classic/rtl/red_pitaya_top.sv:399]
My red_pitaya_top.sv looks like below in that part:
Code: Select all
////////////////////////////////////////////////////////////////////////////////
// House Keeping
////////////////////////////////////////////////////////////////////////////////
//my
//Define new signals
logic [31:0] custom_reg_0;
logic [31:0] custom_reg_1;
logic [31:0] custom_reg_2;
logic [31:0] custom_reg_3;
red_pitaya_id i_id (
// system signals
.clk_i (adc_clk ), // clock
.rstn_i (adc_rstn), // reset - active low
// global configuration
.digital_loop (digital_loop),
//my
//In house keeping define 4 new signals
.custom_reg_0 (custom_reg_0),
.custom_reg_1 (custom_reg_1),
.custom_reg_2 (custom_reg_2),
.custom_reg_3 (custom_reg_3),
// System bus
.sys_addr (sys[0].addr ),
.sys_wdata (sys[0].wdata),
.sys_wen (sys[0].wen ),
.sys_ren (sys[0].ren ),
.sys_rdata (sys[0].rdata),
.sys_err (sys[0].err ),
.sys_ack (sys[0].ack )
);
Since original project created under Ubuntu and Vivado 2017.2, I made it from Ubuntu and Vivado 2017.2 in GUI mode, saved the project and copied to Windows 10 Vivado 2017.4, it went fine for previous examples.
I will appreciate your support.
Or do you have another how to define custom register such way that I can use monitor command from red pitaya?