GPIO Control for RedPi 125-14 with alpine linux by Pavel Demin

[Mechatron]

Greetings,
I'm new to working with the RedPitaya Board and I have no clue about fpga programming,
so I'm trying to to use the "Vector Network Analyzer" by Pavel Demin to adapt it to my needs.
(Cause I need the HF Analog output)
However I do also need to read the status of one of the 16 DIO from E1 and
I want to use the libgpiod library for that.
I've added this function to the vna.c:

Code: Select all

static int read_gpio_value(int gpio_chip_base, int pin_num) {
    char chipname[20];
    sprintf(chipname, "gpiochip%d", gpio_chip_base);
    struct gpiod_chip *chip = gpiod_chip_open_by_name(chipname);
    if (!chip) {
		log_perror("Open chip failed");
        return -1;
    }
    struct gpiod_line *line = gpiod_chip_get_line(chip, pin_num);
    if (!line) {
        gpiod_chip_close(chip);
        return -1;
    }
    int ret = gpiod_line_request_input(line, "read_gpio_value");
    if (ret < 0) {
        gpiod_line_release(line);
        gpiod_chip_close(chip);
        return -1;
    }

    int value = gpiod_line_get_value(line);

    gpiod_line_release(line);
    gpiod_chip_close(chip);

    return value;
}

And I'm using the function like this

Code: Select all

#include <gpiod.h>
...
#define BASE_GPIO_0 	0
...
int pin = 0;
		  
do
{
	ret_val = read_gpio_value(BASE_GPIO_0, pin );
	sprintf(buf,"Pin %d = %d", pin , ret_val);
	logMessage(buf);
	pin ++; 
}while(i<=118);

I wasn't sure which of the 118 pins corresponds to the 16 DIO pins on the E1
So I've put a jumper from one of the first two 3V3 powersupply pins to one of the 16 Dio Pins (I've tried all of'em)
However, I can read their status without an error, but the values stay the same don't matter what I do with the pins. Does anybody know what might be the problem ?
Thank you in advance.

The pin reading looks like this btw. :

Pin 0 = 0
Pin 1 = 1
Pin 2 = 0
Pin 3 = 0
Pin 4 = 1
Pin 5 = 1
Pin 6 = 0
Request line as input failed: Invalid argument
Pin 7 = -1
Request line as input failed: Invalid argument
Pin 8 = -1
Pin 9 = 0
Pin 10 = 0
Pin 11 = 0
Pin 12 = 0
Pin 13 = 0
Pin 14 = 0
Pin 15 = 0
Pin 16 = 0
Pin 17 = 0
Pin 18 = 0
Pin 19 = 0
Pin 20 = 0
Pin 21 = 0
Pin 22 = 0
Pin 23 = 0
Pin 24 = 0
Pin 25 = 0
Pin 26 = 0
Pin 27 = 0
Pin 28 = 0
Pin 29 = 0
Pin 30 = 0
Pin 31 = 0
Pin 32 = 0
Pin 33 = 0
Pin 34 = 0
Pin 35 = 0
Pin 36 = 0
Pin 37 = 0
Pin 38 = 0
Pin 39 = 0
Pin 40 = 0
Pin 41 = 0
Pin 42 = 0
Pin 43 = 0
Pin 44 = 0
Pin 45 = 0
Pin 46 = 0
Pin 47 = 0
Pin 48 = 0
Pin 49 = 1
Pin 50 = 0
Pin 51 = 0
Pin 52 = 0
Pin 53 = 0
Request line as input failed: Resource busy
Pin 54 = -1
Pin 55 = 0
Pin 56 = 0
Pin 57 = 0
Pin 58 = 0
Pin 59 = 0
Pin 60 = 0
Pin 61 = 0
Pin 62 = 0
Pin 63 = 0
Pin 64 = 0
Pin 65 = 0
Pin 66 = 0
Pin 67 = 0
Pin 68 = 0
Pin 69 = 0
Pin 70 = 0
Pin 71 = 0
Pin 72 = 0
Pin 73 = 0
Pin 74 = 0
Pin 75 = 0
Pin 76 = 0
Pin 77 = 0
Pin 78 = 0
Pin 79 = 0
Pin 80 = 0
Pin 81 = 0
Pin 82 = 0
Pin 83 = 0
Pin 84 = 0
Pin 85 = 0
Pin 86 = 0
Pin 87 = 0
Pin 88 = 0
Pin 89 = 0
Pin 90 = 0
Pin 91 = 0
Pin 92 = 0
Pin 93 = 0
Pin 94 = 0
Pin 95 = 0
Pin 96 = 0
Pin 97 = 0
Pin 98 = 0
Pin 99 = 0
Pin 100 = 0
Pin 101 = 0
Pin 102 = 0
Pin 103 = 0
Pin 104 = 0
Pin 105 = 0
Pin 106 = 0
Pin 107 = 0
Pin 108 = 0
Pin 109 = 0
Pin 110 = 0
Pin 111 = 0
Pin 112 = 0
Pin 113 = 0
Pin 114 = 0
Pin 115 = 0
Pin 116 = 0
Pin 117 = 0

[Mechatron]

Ok aparently I need to adapt the devicetree.dtb to activate the gpio pins (the fpga part includes them already)
This is the decompiled devicetree content, I guess I have to adapt the gpio@e000a000 part.
Any hints ?

Code: Select all

/dts-v1/;

/ {
	#address-cells = <0x01>;
	#size-cells = <0x01>;
	compatible = "xlnx,zynq-7000";

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x00>;
			clocks = <0x01 0x03>;
			clock-latency = <0x3e8>;
			cpu0-supply = <0x02>;
			operating-points = <0xa2c2a 0xf4240 0x51615 0xf4240>;
			phandle = <0x10>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x01>;
			clocks = <0x01 0x03>;
			phandle = <0x12>;
		};
	};

	fpga-full {
		compatible = "fpga-region";
		fpga-mgr = <0x03>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges;
	};

	pmu@f8891000 {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;
		interrupt-parent = <0x04>;
		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
	};

	fixedregulator {
		compatible = "regulator-fixed";
		regulator-name = "VCCPINT";
		regulator-min-microvolt = <0xf4240>;
		regulator-max-microvolt = <0xf4240>;
		regulator-boot-on;
		regulator-always-on;
		phandle = <0x02>;
	};

	replicator {
		compatible = "arm,coresight-static-replicator";
		clocks = <0x01 0x1b 0x01 0x2e 0x01 0x2f>;
		clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

		out-ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;

				endpoint {
					remote-endpoint = <0x05>;
					phandle = <0x0c>;
				};
			};

			port@1 {
				reg = <0x01>;

				endpoint {
					remote-endpoint = <0x06>;
					phandle = <0x0b>;
				};
			};
		};

		in-ports {

			port {

				endpoint {
					remote-endpoint = <0x07>;
					phandle = <0x0d>;
				};
			};
		};
	};

	amba {
		u-boot,dm-pre-reloc;
		compatible = "simple-bus";
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		interrupt-parent = <0x04>;
		ranges;

		adc@f8007100 {
			compatible = "xlnx,zynq-xadc-1.00.a";
			reg = <0xf8007100 0x20>;
			interrupts = <0x00 0x07 0x04>;
			interrupt-parent = <0x04>;
			clocks = <0x01 0x0c>;

			xlnx,channels {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				channel@0 {
					reg = <0x00>;
				};

				channel@1 {
					reg = <0x01>;
				};

				channel@2 {
					reg = <0x02>;
				};

				channel@9 {
					reg = <0x09>;
				};

				channel@10 {
					reg = <0x0a>;
				};
			};
		};

		can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x01 0x13 0x01 0x24>;
			clock-names = "can_clk\0pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0x00 0x1c 0x04>;
			interrupt-parent = <0x04>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		can@e0009000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x01 0x14 0x01 0x25>;
			clock-names = "can_clk\0pclk";
			reg = <0xe0009000 0x1000>;
			interrupts = <0x00 0x33 0x04>;
			interrupt-parent = <0x04>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		gpio@e000a000 {
			compatible = "xlnx,zynq-gpio-1.0";
			#gpio-cells = <0x02>;
			clocks = <0x01 0x2a>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x14 0x04>;
			reg = <0xe000a000 0x1000>;
			emio-gpio-width = <0x40>;
			gpio-mask-high = <0x00>;
			[b]gpio-mask-low = <0x5600>;[/b]
			phandle = <0x0a>;
		};

		i2c@e0004000 {
			compatible = "cdns,i2c-r1p10";
			status = "okay";
			clocks = <0x01 0x26>;
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x19 0x04>;
			reg = <0xe0004000 0x1000>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clock-frequency = <0x61a80>;

			eeprom@50 {
				compatible = "24c64";
				size = <0x2000>;
				pagesize = <0x20>;
				reg = <0x50>;
			};
		};

		i2c@e0005000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <0x01 0x27>;
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x30 0x04>;
			reg = <0xe0005000 0x1000>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
		};

		interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <0x03>;
			interrupt-controller;
			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
			num_cpus = <0x02>;
			num_interrupts = <0x60>;
			phandle = <0x04>;
		};

		cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xf8f02000 0x1000>;
			interrupts = <0x00 0x02 0x04>;
			arm,data-latency = <0x03 0x02 0x02>;
			arm,tag-latency = <0x02 0x02 0x02>;
			cache-unified;
			cache-level = <0x02>;
		};

		memory-controller@f8006000 {
			compatible = "xlnx,zynq-ddrc-a05";
			reg = <0xf8006000 0x1000>;
		};

		ocmc@f800c000 {
			compatible = "xlnx,zynq-ocmc-1.0";
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x03 0x04>;
			reg = <0xf800c000 0x1000>;
		};

		serial@e0000000 {
			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
			status = "okay";
			clocks = <0x01 0x17 0x01 0x28>;
			clock-names = "uart_clk\0pclk";
			reg = <0xe0000000 0x1000>;
			interrupts = <0x00 0x1b 0x04>;
			cts-override;
			device_type = "serial";
			port-number = <0x00>;
		};

		serial@e0001000 {
			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
			status = "okay";
			clocks = <0x01 0x18 0x01 0x29>;
			clock-names = "uart_clk\0pclk";
			reg = <0xe0001000 0x1000>;
			interrupts = <0x00 0x32 0x04>;
			cts-override;
			device_type = "serial";
			port-number = <0x01>;
		};

		spi@e0006000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0006000 0x1000>;
			status = "okay";
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x1a 0x04>;
			clocks = <0x01 0x19 0x01 0x22>;
			clock-names = "ref_clk\0pclk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			is-decoded-cs = <0x00>;
			num-cs = <0x03>;
		};

		spi@e0007000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0007000 0x1000>;
			status = "okay";
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x31 0x04>;
			clocks = <0x01 0x1a 0x01 0x23>;
			clock-names = "ref_clk\0pclk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			is-decoded-cs = <0x00>;
			num-cs = <0x01>;

			spidev@0 {
				compatible = "spidev";
				reg = <0x00>;
				spi-max-frequency = <0x989680>;
			};
		};

		spi@e000d000 {
			clock-names = "ref_clk\0pclk";
			clocks = <0x01 0x0a 0x01 0x2b>;
			compatible = "xlnx,zynq-qspi-1.0";
			status = "disabled";
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x13 0x04>;
			reg = <0xe000d000 0x1000>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
		};

		memory-controller@e000e000 {
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			status = "disabled";
			clock-names = "memclk\0apb_pclk";
			clocks = <0x01 0x0b 0x01 0x2c>;
			compatible = "arm,pl353-smc-r2p1\0arm,primecell";
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x12 0x04>;
			ranges;
			reg = <0xe000e000 0x1000>;

			flash@e1000000 {
				status = "disabled";
				compatible = "arm,pl353-nand-r2p1";
				reg = <0xe1000000 0x1000000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
			};

			flash@e2000000 {
				status = "disabled";
				compatible = "cfi-flash";
				reg = <0xe2000000 0x2000000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
			};
		};

		ethernet@e000b000 {
			compatible = "cdns,zynq-gem\0cdns,gem";
			reg = <0xe000b000 0x1000>;
			status = "okay";
			interrupts = <0x00 0x16 0x04>;
			clocks = <0x01 0x1e 0x01 0x1e 0x01 0x0d>;
			clock-names = "pclk\0hclk\0tx_clk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phy-mode = "rgmii-id";
			xlnx,ptp-enet-clock = <0x69f6bcb>;
		};

		ethernet@e000c000 {
			compatible = "cdns,zynq-gem\0cdns,gem";
			reg = <0xe000c000 0x1000>;
			status = "disabled";
			interrupts = <0x00 0x2d 0x04>;
			clocks = <0x01 0x1f 0x01 0x1f 0x01 0x0e>;
			clock-names = "pclk\0hclk\0tx_clk";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
		};

		mmc@e0100000 {
			compatible = "arasan,sdhci-8.9a";
			status = "okay";
			clock-names = "clk_xin\0clk_ahb";
			clocks = <0x01 0x15 0x01 0x20>;
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x18 0x04>;
			reg = <0xe0100000 0x1000>;
			xlnx,has-cd = <0x01>;
			xlnx,has-power = <0x00>;
			xlnx,has-wp = <0x01>;
		};

		mmc@e0101000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin\0clk_ahb";
			clocks = <0x01 0x16 0x01 0x21>;
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x2f 0x04>;
			reg = <0xe0101000 0x1000>;
		};

		slcr@f8000000 {
			u-boot,dm-pre-reloc;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
			reg = <0xf8000000 0x1000>;
			ranges;
			phandle = <0x08>;

			clkc@100 {
				u-boot,dm-pre-reloc;
				#clock-cells = <0x01>;
				compatible = "xlnx,ps7-clkc";
				fclk-enable = <0x00>;
				clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
				reg = <0x100 0x100>;
				ps-clk-frequency = <0x1fca055>;
				phandle = <0x01>;
			};

			rstc@200 {
				compatible = "xlnx,zynq-reset";
				reg = <0x200 0x48>;
				#reset-cells = <0x01>;
				syscon = <0x08>;
			};

			pinctrl@700 {
				compatible = "xlnx,pinctrl-zynq";
				reg = <0x700 0x200>;
				syscon = <0x08>;
			};
		};

		dmac@f8003000 {
			compatible = "arm,pl330\0arm,primecell";
			reg = <0xf8003000 0x1000>;
			interrupt-parent = <0x04>;
			interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
			interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;
			#dma-cells = <0x01>;
			#dma-channels = <0x08>;
			#dma-requests = <0x04>;
			clocks = <0x01 0x1b>;
			clock-names = "apb_pclk";
		};

		devcfg@f8007000 {
			compatible = "xlnx,zynq-devcfg-1.0";
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x08 0x04>;
			reg = <0xf8007000 0x100>;
			clocks = <0x01 0x0c 0x01 0x0f 0x01 0x10 0x01 0x11 0x01 0x12>;
			clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3";
			syscon = <0x08>;
			phandle = <0x03>;
		};

		efuse@f800d000 {
			compatible = "xlnx,zynq-efuse";
			reg = <0xf800d000 0x20>;
		};

		timer@f8f00200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xf8f00200 0x20>;
			interrupts = <0x01 0x0b 0x301>;
			interrupt-parent = <0x04>;
			clocks = <0x01 0x04>;
		};

		timer@f8001000 {
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;
			compatible = "cdns,ttc";
			clocks = <0x01 0x06>;
			reg = <0xf8001000 0x1000>;
		};

		timer@f8002000 {
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;
			compatible = "cdns,ttc";
			clocks = <0x01 0x06>;
			reg = <0xf8002000 0x1000>;
		};

		timer@f8f00600 {
			interrupt-parent = <0x04>;
			interrupts = <0x01 0x0d 0x301>;
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xf8f00600 0x20>;
			clocks = <0x01 0x04>;
		};

		usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
			status = "okay";
			clocks = <0x01 0x1c>;
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x15 0x04>;
			reg = <0xe0002000 0x1000>;
			phy_type = "ulpi";
			dr_mode = "host";
			usb-phy = <0x09>;
			xlnx,phy-reset-gpio = <0x0a 0x30 0x00>;
		};

		usb@e0003000 {
			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
			status = "disabled";
			clocks = <0x01 0x1d>;
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x2c 0x04>;
			reg = <0xe0003000 0x1000>;
			phy_type = "ulpi";
		};

		watchdog@f8005000 {
			clocks = <0x01 0x2d>;
			compatible = "cdns,wdt-r1p2";
			interrupt-parent = <0x04>;
			interrupts = <0x00 0x09 0x01>;
			reg = <0xf8005000 0x1000>;
			timeout-sec = <0x0a>;
		};

		etb@f8801000 {
			compatible = "arm,coresight-etb10\0arm,primecell";
			reg = <0xf8801000 0x1000>;
			clocks = <0x01 0x1b 0x01 0x2e 0x01 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x0b>;
						phandle = <0x06>;
					};
				};
			};
		};

		tpiu@f8803000 {
			compatible = "arm,coresight-tpiu\0arm,primecell";
			reg = <0xf8803000 0x1000>;
			clocks = <0x01 0x1b 0x01 0x2e 0x01 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

			in-ports {

				port {

					endpoint {
						remote-endpoint = <0x0c>;
						phandle = <0x05>;
					};
				};
			};
		};

		funnel@f8804000 {
			compatible = "arm,coresight-static-funnel\0arm,primecell";
			reg = <0xf8804000 0x1000>;
			clocks = <0x01 0x1b 0x01 0x2e 0x01 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x0d>;
						phandle = <0x07>;
					};
				};
			};

			in-ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;

					endpoint {
						remote-endpoint = <0x0e>;
						phandle = <0x11>;
					};
				};

				port@1 {
					reg = <0x01>;

					endpoint {
						remote-endpoint = <0x0f>;
						phandle = <0x13>;
					};
				};

				port@2 {
					reg = <0x02>;

					endpoint {
					};
				};
			};
		};

		ptm@f889c000 {
			compatible = "arm,coresight-etm3x\0arm,primecell";
			reg = <0xf889c000 0x1000>;
			clocks = <0x01 0x1b 0x01 0x2e 0x01 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
			cpu = <0x10>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x11>;
						phandle = <0x0e>;
					};
				};
			};
		};

		ptm@f889d000 {
			compatible = "arm,coresight-etm3x\0arm,primecell";
			reg = <0xf889d000 0x1000>;
			clocks = <0x01 0x1b 0x01 0x2e 0x01 0x2f>;
			clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
			cpu = <0x12>;

			out-ports {

				port {

					endpoint {
						remote-endpoint = <0x13>;
						phandle = <0x0f>;
					};
				};
			};
		};
	};

	amba_pl {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		compatible = "simple-bus";
		ranges;

		axi_sts_register@40000000 {
			clock-names = "aclk";
			clocks = <0x14>;
			compatible = "xlnx,axi-sts-register-1.0";
			reg = <0x40000000 0x1000>;
		};

		misc_clk_0 {
			#clock-cells = <0x00>;
			clock-frequency = <0x7735940>;
			compatible = "fixed-clock";
			phandle = <0x14>;
		};
	};

	chosen {
		bootargs = "console=ttyPS0,115200 earlyprintk earlycon";
		stdout-path = "serial0:115200n8";
	};

	phy0 {
		#phy-cells = <0x00>;
		compatible = "ulpi-phy";
		reg = <0xe0002000 0x1000>;
		view-port = <0x170>;
		drv-vbus;
		phandle = <0x09>;
	};

	pps {
		compatible = "pps-gpio";
		gpios = <0x0a 0x36 0x00>;
		capture-clear;
	};

	aliases {
		ethernet0 = "/amba/ethernet@e000b000";
		i2c0 = "/amba/i2c@e0004000";
		serial0 = "/amba/serial@e0000000";
		serial1 = "/amba/serial@e0001000";
		spi0 = "/amba/spi@e0006000";
		spi1 = "/amba/spi@e0007000";
	};

	memory {
		device_type = "memory";
		reg = <0x00 0x20000000>;
	};
};

[pavel]

The FPGA configuration of the VNA application does not have input pins.

If you do not want to change the FPGA configuration, then the only option is to use an external module with an I2C or SPI GPIO expander and connect it to the I2C or SPI pins of the Red Pitaya board.

If you only need one input, then maybe the SPI (MISO) input of the extension connector E2 could be used for that.

[Mechatron]

Thank you for the clarification