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Re: Generation of a signal from a trigger
Posted: Fri Oct 20, 2023 1:51 pm
by redpitaya
Great to hear that it is working as expected!
Thank you for mentioning the solution. This will help other users with the same problem.
Good luck with your projects!
Re: Generation of a signal from a trigger
Posted: Tue Oct 24, 2023 12:35 pm
by TheGeri
redpitaya wrote: ↑Fri Oct 20, 2023 11:50 am
Hello TheGeri,
I will check this out.
If you are using the 2.00 OS version, I apologise. I thought that the 2.00 FGPA update was already applied to the tutorials, however, I double-checked and noticed that I forgot to merge it with the main branch. Anyway, the tutorials should be updated for the 2.00 OS now:
https://redpitaya-knowledge-base.readth ... s/top.html
Good afternoon,
Have you been able to investigate the case of the error I mentioned, where the Vivado program was closed during synthesis process? Following the procedure from this example:
https://redpitaya-knowledge-base.readth ... Rider.html I encounter the same problem, and the Vivado program closes. I should mention that I also modified the
make_project.tcl file in the
/RedPitaya-FPGA/prj/Examples folder to use the
Knight_rider project:
Code: Select all
# Uncomment the example you want to run
#set project_name "Led_blink"
set project_name "Knight_rider"
#set project_name "Stopwatch"
#set project_name "Frequency_counter"
#set project_name "Simple_moving_average"
#set project_name "Vga_draw"
#set project_name "Vga_game"
#set project_name "Vga_image"
cd $project_name
source make_project.tcl
I have the same error log that I provided to you before. Could it be an installation error with Vivado or sth like this? I followed the same process as here:
https://redpitaya-knowledge-base.readth ... fpga1.html, using WSL and installing the Linux Self Extracting Web Installer that was available.
I appreciate any kind of help or advice. Thanks you in advance!
Re: Generation of a signal from a trigger
Posted: Mon Oct 30, 2023 2:20 pm
by redpitaya
Hello TheGeri,
I apologise for the late reply.
Sorry, I have been busy with other projects that needed immediate attention. I will test the functionality of all FPGA examples this week.