Controlling new FPGA program from PyRPL

[fpgaSim123]

Hey guys,

I recently implemented an FPGA program to sum signals from the two analog input channels and it worked wonderfully (I can see in1 + in2 on the oscilloscope)! The thing is, it works as soon as I run the bit-stream file on the Red Pitaya, but I would like to 'enable' and 'disable' this by giving commands through a python script.

I want to do something like what one does with the ASGs: give a command using the PyRPL library to output a certain waveform, turn it off to abort the process. I would also like to give a command saying add('in1','in2'). Perhaps even go further by doing some subtraction beforehand : define a parameter in1_bg (background correction) and in2_bg, then give the command add('in1','in1_bg','in2','in2_bg') which would do: (in1 - in1_bg) + (in2 - in2_bg). These background correction terms would effectively be constant values that would be determined beforehand and subtracted continuously from the input channels before summing (or along with the summation process).

Could someone tell me how I could do this? Should I create a new module called 'adder.py' and define something there? I tried to take a look at the other software modules (I currently replace the MIMO PID on the FPGA with the new adder module) but I am intimidated by the unending lines of code

Do give some suggestions. Thanks!

[redpitaya]

Hello fpgaSim123,

Perhaps the easiest way is to create a signal bypass around your component. Then you have a specific register where you decide whether to route the signal through your component or around it. To enable/disable the bypass just write to a specific address.

You can then go further by implementing multiple bypasses or having a specific register value to select which "option" to take. For example, writing a 0 into your register would result in a bypass of the whole component. A 1 would result in IN1 + IN2, a 2 in IN1 - IN2, ..., a 6 may result in (IN1 - const_1) + (IN2 - const_2). You can see how to implement a bypass in Verilog in this project in the "red_pitaya_top" file. Check lines near the end of project with proc_i and proc_o, then there should be a definition of the proc_i and proc_o somewhere around line 180 (search for proc_i). You can use this, but one level lower - inside your Added component (or perhaps by creating a submodule for you adder component where you copy the current code and then implement the bypass one level higher).
https://lniv.fe.uni-lj.si/redpitaya/redpitaya094.htm

The bypass register is in this case implemented in the "red_pitaya_hk" component on address 0xC (digital loopback): https://redpitaya.readthedocs.io/en/lat ... v0.94.html

I hope this helps.