PID Integrator Hold

Applications, development tools, FPGA, C, WEB
ClaireE47
Posts: 20
Joined: Thu Oct 02, 2014 8:26 am

Re: PID Integrator Hold

Post by ClaireE47 » Mon Dec 01, 2014 4:23 am

Hey, so a slight update. I tried to add a synchronisation step to the PID block Verilog code, but the PID is still not locking. I've attached my (unsuccessful) addition and will keep trying - if anyone has any suggestions, they would be greatly appreciated.

Claire
(Note: pid_hold_pin is the asynchronous input)

Code: Select all

// Synchronise Hold Pin 

reg [2-1:0] pid_hold_shift;
reg 		pid_hold_next;
reg		    pid_hold_final;

always @(posedge clk_i) begin
    if (rstn_i == 1'b0) begin
	   pid_hold_shift <= 2'b0;
       pid_hold_next <= 1'b0;
       pid_hold_final <= 1'b0;
    end
    else begin
        pid_hold_shift <= {pid_hold_shift[0], pid_hold_pin};
        pid_hold_next <= pid_hold_shift[1];
    
        if (pid_hold_next != pid_hold_final)
            pid_hold_final <= pid_hold_next;
    end
end

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: PID Integrator Hold

Post by Nils Roos » Thu Dec 04, 2014 9:36 pm

Hi Claire,
I have adapted your pid locking changes into my working design, and I found that it is behaving exactly as I would have expected.

There was one small detail that caused me puzzlement at first, but that has nothing to do with your additions. It seems that the external trigger input should have a pull-down resistor as per design settings, but hasn't in actuality.
It floats and more often than not reads as logical high, thus causing spurious triggers (or pid locks in your case) when not tied to GND.

But otherwise the pid lock is working fine. Keep it up ;O)
Nils

ClaireE47
Posts: 20
Joined: Thu Oct 02, 2014 8:26 am

Re: PID Integrator Hold

Post by ClaireE47 » Mon Dec 08, 2014 5:32 am

It works!!! Thank you so much Nils Roos - your help was invaluable.

In Verilog, the _top.v, _pid.v, _pid_block.v and constraints were altered. There are quite a few additions throughout the C and HTML for the software trigger.
I can attach the code for anyone who is interested - what is the best way to do that? Simply display the code in the forum as done previously? Or would the folder somewhere be better?

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: PID Integrator Hold

Post by Nils Roos » Tue Dec 09, 2014 2:09 am

Glad I could help :)

Posting all your changes here would be a bit awkward to clone. Zipping your whole sourcetree and putting a dropbox link or similar here works ok, or maybe commit it to your github fork - assuming you got the sources that way in the first place.

ClaireE47
Posts: 20
Joined: Thu Oct 02, 2014 8:26 am

Re: PID Integrator Hold

Post by ClaireE47 » Tue Dec 09, 2014 11:48 pm

Hey, this has my edits to the C code (Applications/MyPID/src) and the HTML (Applications/MyPID/index.html) for the software trigger, and the Verilog edits (FPGA/release1/fpga/code/).

https://www.dropbox.com/sh/rwjmzs183ls9 ... AwFZa?dl=0

fromage
Posts: 10
Joined: Wed Jul 02, 2014 9:05 am

Re: PID Integrator Hold

Post by fromage » Tue Mar 10, 2015 1:43 pm

Hey ClaireE47
I would like to use your sample and hold PID. But I don’t really know where to start.
It would be really nice if you could give me a short guide what I have to do to use the hold feature you introduced in the PID.
Cheers Florian

ClaireE47
Posts: 20
Joined: Thu Oct 02, 2014 8:26 am

Re: PID Integrator Hold

Post by ClaireE47 » Wed Mar 11, 2015 3:55 am

Hi Florian,

Have you done anything with modifying the RP code before?
If you just want to use one of the GPIO pins as a hardware trigger for the hold, then the only part of the code you will need to change is the Verilog FPGA code. I've included the 4 Verilog files that I altered (pid.v, pid_block.v,top.v and the constraints) in the post above. In order to compile the Verilog code and upload it, there is quite a process involved but it's very well described in these threads:
viewtopic.php?f=14&t=49
viewtopic.php?f=8&t=42
There is also a bit of explanation on the RP wiki (pretty minimal though for the FPGA development). On a side note, I ran all of my changes from Linux. I have no idea where to start for other operating systems sorry.

If you want the software trigger, then you also need to change the controller C code (also attached in the post above). The compilation process for the C is simpler and described quite well in the RP Wiki, as is the compilation of the changes to the HTML to make the check box for the trigger on the GUI.

I have a short document that I wrote for my own reference that works well for me when it comes to compilation. I'll attach it when I get a chance (I need to get it off another computer).

Claire

ClaireE47
Posts: 20
Joined: Thu Oct 02, 2014 8:26 am

Re: PID Integrator Hold

Post by ClaireE47 » Tue Mar 17, 2015 12:43 am

Hi Florian,

Hope this helps!

Claire
You do not have the required permissions to view the files attached to this post.

fromage
Posts: 10
Joined: Wed Jul 02, 2014 9:05 am

Re: PID Integrator Hold

Post by fromage » Sat May 23, 2015 2:14 pm

Hi Claire,
Sorry for the late response but finally I managed to compile your code and run it on RP.
After I managed a compile the git code, as Claire said, described in viewtopic.php?f=14&t=49 everything was straight forward.
  • Just copy Claires code into den RedPitaya folder cloned from git and compile it.
  • For the App I only had to add MyPID to the makefile in the Applications folder and copy the "fpga.bit" file from the default PID app int the MYPID folder.
I would like now to connect a TTL to one of the GPIO pins to tell the PID when to hold and when to sample.
Is this possible? How would I do that?
Thanks for your help
Florian

ClaireE47
Posts: 20
Joined: Thu Oct 02, 2014 8:26 am

Re: PID Integrator Hold

Post by ClaireE47 » Sat May 23, 2015 11:03 pm

Hi Florian,

I'm really glad that the code has been working for you. The hardware GPIO should be all set up by the code already. To use it, it triggers the hold for at TTL high signal.
The 2 triggers are DIO0_P and DIO1_P (see attached image of the board). The DIO0_P pin is attached to the analog 1 output and the DIO1_P pin is related to the analog 2 output.

I used a jumper breadboard wire (some like this: https://www.adafruit.com/products/266) to isolate the 2 pins, and then make a connection to a BNC. I'm not sure if RP has made an extension connector or anything yet. I saw that they were planning it at one point.

Hope that helps!
Claire

Image

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