Hi Florian,
Have you done anything with modifying the RP code before?
If you just want to use one of the GPIO pins as a hardware trigger for the hold, then the only part of the code you will need to change is the Verilog FPGA code. I've included the 4 Verilog files that I altered (pid.v, pid_block.v,top.v and the constraints) in the post above. In order to compile the Verilog code and upload it, there is quite a process involved but it's very well described in these threads:
viewtopic.php?f=14&t=49
viewtopic.php?f=8&t=42
There is also a bit of explanation on the RP wiki (pretty minimal though for the FPGA development). On a side note, I ran all of my changes from Linux. I have no idea where to start for other operating systems sorry.
If you want the software trigger, then you also need to change the controller C code (also attached in the post above). The compilation process for the C is simpler and described quite well in the RP Wiki, as is the compilation of the changes to the HTML to make the check box for the trigger on the GUI.
I have a short document that I wrote for my own reference that works well for me when it comes to compilation. I'll attach it when I get a chance (I need to get it off another computer).
Claire