Help: Reading/Writing Data to 0x40600000 to 0x406fffff

[jmh019]

If this is posted to the wrong forum, feel free to move it.

I want to try to read and write data to the addresses 0x40600000 to 0x406fffff, but I have not had much success. I tried creating a module specifically tailored to reading and writing data to that address space:

Code: Select all

module red_pitaya_free
(
   // signals
   input                 clk_i           ,  //!< processing clock
   input                 rstn_i          ,  //!< processing reset - active low


   // system bus
   input                 sys_clk_i       ,  //!< bus clock
   input                 sys_rstn_i      ,  //!< bus reset - active low
   input      [ 32-1: 0] sys_addr_i      ,  //!< bus address
   input      [ 32-1: 0] sys_wdata_i     ,  //!< bus write data
   input      [  4-1: 0] sys_sel_i       ,  //!< bus write byte select
   input                 sys_wen_i       ,  //!< bus write enable
   input                 sys_ren_i       ,  //!< bus read enable
   output reg [ 32-1: 0] sys_rdata_o     ,  //!< bus read data
   output reg            sys_err_o       ,  //!< bus error indicator
   output reg            sys_ack_o          //!< bus acknowledge signal
);

//---------------------------------------------------------------------------------
//
//  System bus connection

reg[31:0] data;

always @(posedge sys_clk_i) begin
   if (sys_rstn_i == 1'b0) begin
      data = 32'h0;
   end
   else begin
      if (sys_wen_i) begin
         data  <= sys_wdata_i[32-1:0] ;
      end
   end
end





always @(*) begin
   sys_err_o <= 1'b0 ;

   casez (sys_addr_i[20:0])
       20'h0????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h1????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h2????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h3????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h4????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h5????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h6????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h7????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h8????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'h9????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'ha????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'hb????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'hc????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'hd????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'he????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end
       20'hf????: begin sys_ack_o <= 1'b1;          sys_rdata_o <= {data}                        ; end                                                                          
       default : begin sys_ack_o <= 1'b1;          sys_rdata_o <=  32'h0                                               ; end
   endcase
end

endmodule

However, I am not sure how to tell the Red Pitaya to specifically read and write to any addresses without commenting out the wire sys_addr and sys_wdata in red_pitaya_top.v and hard coding the values like so:

Code: Select all

red_pitaya_free i_free
(
  .clk_i            (adc_clk), // clock
  .rstn_i           (adc_rstn), // reset - active low

  // System bus
  .sys_clk_i        ( sys_clk ), // clock
  .sys_rstn_i       ( sys_rstn ), // reset - active low
  .sys_addr_i       ( /*sys_addr*/ 32'h40600000 ), // address
  .sys_wdata_i      ( /*sys_wdata*/ 32'h1fff ), // write data
  .sys_sel_i        ( sys_sel ), // write byte select
  .sys_wen_i        ( sys_wen[6] ), // write enable
  .sys_ren_i        ( sys_ren[6] ), // read enable
  .sys_rdata_o      ( sys_rdata[ 6*32+31: 6*32]), // read data
  .sys_err_o        ( sys_err[6] ), // error indicator
  .sys_ack_o        ( sys_ack[6] ) // acknowledge signal
);

After building the .bit file and loading it into the fpga, I use the monitor tool for 0x40600000 and I get:

Code: Select all

redpitaya> monitor 0x40600000
0x000000cc

That result makes no sense to me. Next, I tried to store 0x00001fff value like so:

Code: Select all

redpitaya> monitor 0x40600000 0x00001fff
redpitaya> monitor 0x40600000
0x00001fff

I try it once more with a different value:

Code: Select all

redpitaya> monitor 0x40600000 0x00001ccc
redpitaya> monitor 0x40600000
0x00001fff

I can no longer write to that address for some reason. Also, every 4 bytes has the exact same value for some reason:

Code: Select all

redpitaya> monitor 0x40600000
0x00001fff
redpitaya> monitor 0x40600004
0x00001fff
redpitaya> monitor 0x40600008
0x00001fff
redpitaya> monitor 0x4060000c
0x00001fff
redpitaya> monitor 0x40600010
0x00001fff
redpitaya> monitor 0x406f0010
0x00001fff
redpitaya> monitor 0x406ffff0
0x00001fff
redpitaya> monitor 0x406ffffc
0x00001fff

Any input as to what I am doing wrong would help greatly.

[Nils Roos]

Hi,

some questions first:

Did you deactivate the default values for region 6 in red_pitaya_top.v ?

Code: Select all

assign sys_rdata[ 6*32+31: 6*32] = 32'h0;

assign sys_err[6] = {1{1'b0}} ;
assign sys_ack[6] = {1{1'b1}} ;

Why did you comment out the sys_wdata and sys_addr signals ? These busses carry the write address and data into your module.

You only provide one 32bit storage location (reg data[31:0] but map it to basically the whole 0x406xxxxx region, what is the purpose of your module ?

[jmh019]

Hello!

Yes I commented out those 3 lines because I thought they would be an issue. Is that wrong?

The goal of my module is to write data in the 0x40600000 region that will contain the information for an "ideal" signal. Next, I want to read this data as points for the PID Controller's set point in order to find the error between this "ideal" signal and my input signal.

Should I have defined a 2d vector of 32 bit storage spots like so:

Code: Select all

reg[31:0] data [262143:0]

I calculated about 262144 32bit storages.

[Nils Roos]

Yes I commented out those 3 lines because I thought they would be an issue. Is that wrong?

It would have been wrong to not do it, you were quite right in doing so.

Should I have defined a 2d vector of 32 bit storage spots

Yes, but unfortunately there isn't enough memory capacity inside the FPGA for 256K*32bit. The total internal RAM capacity is 240KB, half of which is already in use.

If you think of fetching the references from external RAM instead, you need to consider that this access would not be finished in time for the next clock-cycle (probably much later).

[jmh019]

Yes, but unfortunately there isn't enough memory capacity inside the FPGA for 256K*32bit. The total internal RAM capacity is 240KB, half of which is already in use.

I am limited by the internal RAM capacity. The biggest possible amount of data I can write and read would be 30k*32bit. Would it be possible for me to somehow read from a file in the Red Pitaya without using C code? C code would be too slow in comparison to verilog.

If you think of fetching the references from external RAM instead, you need to consider that this access would not be finished in time for the next clock-cycle (probably much later).

When you mention external RAM, this is RAM I would have to add to the Red Pitaya right? (sorry I am new to this) About how many clock cycles would it take for just 1 access? Like 5 or 10 cycles?

[Nils Roos]

By external RAM I mean the 512MB main memory. That's the fastest mass storage medium available on board the Red Pitaya. You can't use the filesystem (which is C code) from inside the PL.
Accessing this memory is a bit more difficult to implement and the latency is unpredictable because you share the DDR controller with the OS and userspace applications. If I had to guess, a couple of tens of (ADC clock-) cycles, worst case ?

[jmh019]

Thanks for the responses.

By external RAM I mean the 512MB main memory. That's the fastest mass storage medium available on board the Red Pitaya. You can't use the filesystem (which is C code) from inside the PL.
Accessing this memory is a bit more difficult to implement and the latency is unpredictable because you share the DDR controller with the OS and userspace applications. If I had to guess, a couple of tens of (ADC clock-) cycles, worst case ?

Is there any tips you could give for implementing access to the external RAM? I would like to try reading and writing from there.

Also, is it possible to read and write information to the mini SD card?

[Nils Roos]

My advice is to look through the included IP blocks in Vivado, especially the AXI-themed ones. Fast access to the external RAM is done via the AXI HP interfaces and there probably is something there that you can use.

Use of the SD card by any other means than the OS is impractical, to say the least. The SD card is also quite slow.

[jmh019]

My advice is to look through the included IP blocks in Vivado, especially the AXI-themed ones. Fast access to the external RAM is done via the AXI HP interfaces and there probably is something there that you can use.

I was looking through the IP blocks. I found the one called Axi DMA and I was wondering if that would be the best IP to use for fast access to the external RAM. If so, how would I go about connecting it to the External RAM and the AXI HP interfaces?