Discussions about active development projects
#519 by hmaarrfk
Fri Aug 01, 2014 4:08 pm
Here are a few pointers to implement it on the FPGA:

1. Take a look at the PID blocks. They basically implement some 1st order system modeling :P.
2. Xilinx has a few IP cores that you can probably take advantage of. Browse through them in Vivado.
3. Fixed point. You will have to do your math in Fixed Point notation for speed.
4. This particular FPGA has limited multipliers. A 20th order model would take 40 multipliers if it is running at full speed. You might want to take advantage of their dedicated DSP blocks. They are called DSP48 slices.


Note: feeding adc_a directly to dac_a, I measured a 120ns delay for all frequencies. That indicates that it is all due to pipeline delays in the system. Keep that in mind when designing your models.
#775 by DashPi
Tue Aug 05, 2014 8:01 pm
thanks hmaarrfk!
i have been very busy. I will try that, but first I have to figure out how to address this general purpose fixed point dsp problem.
I don't consider the pipeline delay an issue.

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