I am curious about the "simplified" M_AXI_GP timing diagram. I looked for it without success in The Zynq Book. There are some diagrams in this document http://www.xilinx.com/support/documenta ... _guide.pdf , but as far as I could understand them, they are focusing on transmitting and receiving of a single data byte.
I have tried to deduct how the PS-PL interface is going on the following example. Assume that I want to read the first value of the buffer that stores the samples of the oscilloscope's Channel A. Then, I have to read 4 bytes located at 0x40100000 + 0x10000. I can do it for example with mmap object in Python running on RP. Works fine.
Now, if I look at the FPGA source code (red_pitaya_scope.v), I see that the actual reading is happening here:
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adc_raddr <= sys_addr[RSZ+1:2] ; // address synchronous to clock
adc_a_raddr <= adc_raddr ; // double register
adc_a_rd <= adc_a_buf[adc_a_raddr] ;
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20'h1???? : begin sys_ack <= adc_rd_dv; sys_rdata <= {16'h0, 2'h0,adc_a_rd} ; end
I would really appreciate if someone could explain the relations between system bus signals (sys_ack, sys_rdata etc) with respect to the adc_clk_i clock. That will be also great to read something about this interface, but more friendly rather than 1000 pages Xilinx documents (although I understand that Xilinx docs are the only complete and trustful sources ).
Ruben