OS 0.96 documentation

Just about everything about Red Pitaya
Post Reply
Program
Posts: 27
Joined: Thu Apr 14, 2016 3:14 pm

OS 0.96 documentation

Post by Program » Fri Sep 23, 2016 1:52 pm

Hi everyone, I have recently updated my Red Pitayas to the latest OS version. However, I was disappointed by the lack of documentation describing the new features in this version. It seems that there are now several FPGA bitstreams available and I guess I have to load a separate bitstream for particular applications. How exactly is this done? Also, I haven't found much information regarding the use of the different FPGA configurations. The API only seems to work with the old FPGA version, so how do I control FPGA operation with a C program for the other FPGA bitstreams? I also wondered what the api2 library does as it is not described on the RP Wiki website.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: OS 0.96 documentation

Post by Nils Roos » Sat Sep 24, 2016 8:15 pm

Hi,
all Bazaar-apps (ie all apps that you start through your RedPitaya's homepage) automatically load the bitstream they need.
Applications that use the RP api require the correct bitstream (fpga_0.94.bit) to be loaded before starting.
I have to load a separate bitstream for particular applications. How exactly is this done?
You can load a bitstream from within a C program by opening the file "/dev/xdevcfg" and writing the data into it. On the console you can do "cat xxx.bit > /dev/xdevcfg". Bazaar apps can indicate in their fpga.conf which bitstream they require.
The API only seems to work with the old FPGA version, so how do I control FPGA operation with a C program for the other FPGA bitstreams?
What exactly did you have in mind with "a C program for the other FPGA bitstreams"?

A bit of background story regarding api2 etc. (as I observed it from the outside):
The logic analyzer required a new way of reading data from the GPIOs. With that in mind it was planned to implement a more modern approach for all the Red Pitaya specific peripherals. The fpga design was rebuild from the ground to enable this approach, and the connection to the GPIOs was implemented into it to make the logic analyzer work. The api2 was created to eventually interface with all components using the new approach, again starting with the logic analyzer.
Then development priorities shifted and it now looks increasingly unlikely that the remainder of the Red Pitaya peripherals will be integrated into the api2 and the underlying logic.

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 122 guests