Timing diagram of the PS to PL intefacing

[Ubix2014]

Hi,

I am curious about the "simplified" M_AXI_GP timing diagram. I looked for it without success in The Zynq Book. There are some diagrams in this document http://www.xilinx.com/support/documenta ... _guide.pdf , but as far as I could understand them, they are focusing on transmitting and receiving of a single data byte.

I have tried to deduct how the PS-PL interface is going on the following example. Assume that I want to read the first value of the buffer that stores the samples of the oscilloscope's Channel A. Then, I have to read 4 bytes located at 0x40100000 + 0x10000. I can do it for example with mmap object in Python running on RP. Works fine.

Now, if I look at the FPGA source code (red_pitaya_scope.v), I see that the actual reading is happening here:

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  adc_raddr   <= sys_addr[RSZ+1:2] ; // address synchronous to clock
  adc_a_raddr <= adc_raddr     ; // double register 
  adc_a_rd    <= adc_a_buf[adc_a_raddr] ;

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 20'h1???? : begin sys_ack <= adc_rd_dv;       sys_rdata <= {16'h0, 2'h0,adc_a_rd}              ; end

So, the address of the word in buffer to be read is sys_addr[RSZ+1:2] . Obliviously, this address has to be transmitted before the reading from adc_a_rd => the mmap reading requires at least to adc_clk_i clock cycles. But this is only my guess.

I would really appreciate if someone could explain the relations between system bus signals (sys_ack, sys_rdata etc) with respect to the adc_clk_i clock. That will be also great to read something about this interface, but more friendly rather than 1000 pages Xilinx documents (although I understand that Xilinx docs are the only complete and trustful sources ).

Ruben

[Nils Roos]

Hi Ruben,

here's some fancy ASCII art to demonstrate the timing of reading from the sample buffer:

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              0   1   2   3   4   5   6   7 
adc_clk     _/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\

sys_ren     _____/¯¯¯\______________________
sys_addr    -----<Adr================>------

adc_raddr   ><**><**><Ad><Ad><Ad><Ad><**><** (inside red_pitaya_scope)
adc_a_raddr ><**><**><**><Ad><Ad><Ad><Ad><**  -"-
adc_a_rd    ><**><**><**><**><Da><Da><Da><Da  -"-

sys_ack     _____________________/¯¯¯\______
sys_rdata   ---------<**><**><**><Dat>------

At cycle 0 the read request arrives at the AXI GP0 interface of axi4_slave (fpga/rtl/axi4_slave.sv). When there is no other operation in progress and no request of higher priority pending, the read request will be put on the sys-bus.
The read address and read enable signal will go active at cycle 1, and will be forwarded to the red_pitaya_scope module if the address is in the scope's range. Inside the scope there are four pipeline stages that latch the address and read from the BRAM buffer. At stage four, the data is written to the outgoing data lines and the sys_ack signal is asserted.
This causes the axi4_slave to generate an answer in cycle 6 to the read request that is still in progress on the AXI GP0 interface.

[Ubix2014]

Hi Nils,

Thank you for the comprehensive answer. Could we say that a reading operation takes at least 7 clock cycles?

I am making now a 5 channels pulse counter based on RP ( I will probably make a post here on this project. It is quite interesting: 4ns NIM pulses are level converted then stretched to 20 ns and fed to RP). The pulses are counted over a programmable width counting window (min 1us, max 1s), the result of counting should be stored in a buffer such that the remote PC has an access to this buffer. So, I this is why I need to know how long does it actually takes to make a reading from RP.

BR, Ruben

[Nils Roos]

Hi Ruben,

the only thing you can say about the timing with any certainty is that it takes 7 adc_clk cycles to process a read request inside the fpga and that it will take at least a certain (currently undetermined) amount of time for the request to traverse from the cores to the AXI GP0 port and back.
How long it actually takes depends on some not precisely knowable variables, like system load and clock phase relations. And with the optimizations built into modern processors, it is also difficult to know when a request is launched.