Radar project: help with DMA and the kernel

Just about everything about Red Pitaya
Post Reply
shufu
Posts: 1
Joined: Tue Sep 20, 2016 4:32 pm

Radar project: help with DMA and the kernel

Post by shufu » Tue Jan 17, 2017 9:00 pm

Hello everyone,

Brief introduction: for our undergraduate masters project, my team and I are building an FMCW radar with two channels at S-band and C-band. We are using the Red Pitaya for data acquisition, radar processing, and as a controller for the analog RF frontend which my teammates are working on, while I am in charge of all the development on the Red Pitaya. My goal is to do the radar processing in real time using programmable logic, as the majority of it should be FFTs and FIR filtering. The processing system would mainly be used for running controller software and sending the output data over the network.

I have a little bit of experience in SoC design using the Vivado IP integrator, so I decided to start with Pavel's projects instead of the main ecosystem's FPGA project. I'm using the fast ADCs for acquiring the IF FMCW signals (50kHz bandwidth), which are DDC'd and separated in I/Q signals using Xilinx IP blocks, based on Pavel's SDR tranceiver project.

Now I would like to use the Xilinx DMA engine IP to write the I/Q data to RAM, using the Xilinx DMA drivers and Linux CMA. I read Pavel's post on DMA choice and decided to go with Xilinx's IP because in the end, at multiple stages of the radar processing chain, I will need to write the signal to RAM totaling at least 2 concurrent streams, and from what I understand the Xilinx DMA IP would be most suitable. An example data flow would be [ADC] -> [DDC] -*> [MTI filter] -*> [FFT] -*> [...] with each * being a DMA write.

I currently am trying to do a basic feedback loop test with the DMA IP (without any part of the ADC receiver chain), following the presentation https://forums.xilinx.com/xlnx/attachme ... rivers.pdf.

Right now I've cloned https://github.com/RedPitaya/linux-xlnx to configure the kernel for DMA support (enabling Xilinx DMA drivers and CMA), but this is all really new to me and I'd greatly appreciate some guidance here, such as what exactly should I enable in Kconfig and how to build the kernel for the Red Pitaya, or other steps that I may have missed.

Any other feedback in general would be a huge help! At the moment I am just using various resources on the internet. I don't have anyone at my university to help me with this and it's mostly new territory for me, so I am starting to feel a little lost.

Thanks for your time,
Martin

dl3hm
Posts: 3
Joined: Wed Dec 07, 2016 8:34 pm

Re: Radar project: help with DMA and the kernel

Post by dl3hm » Wed Jan 18, 2017 7:55 pm

I have done some research on red pitaya DMA. Maybe the following links are helpful to you:

http://www.fpgadeveloper.com/2014/08/us ... ivado.html

[url=http://lauri.v%C3%B5sandi.com/hdl/zynq/xilinx-dma.html]http://lauri.võsandi.com/hdl/zynq/xilinx-dma.html[/url]

These two tutorial's are not specific to the red pitaya, but especially the second one should be usable.

My personal conclusion was to stick with the code of Pavel, especially with the dac_player project. This project implements a ring buffer, which is essential for continous operation. IMHO the Xilinx DMA cores do not.

Harald, dl3hm

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 2 guests