Connecting Ethernet PHY to PL

[redpitaya_htw]

Hi,

i'm using VIVADO 2015.4 and i'm currently trying to connect the Ethernet PHY with the PL and have a problem:

Adding the PHY into the constraint file with:

set_property IOSTANDARD LVCMOS18 [get_ports {RX_D3}]
set_property PACKAGE_PIN A15 [get_ports {RX_D3}] ### <---- this is 283

leads to following critical warning:

[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid [".../red_pitaya.xdc":283]

Are anybody able to help me in this matter?

[Nils Roos]

Hi,

the pins that belong to MIO signals can not (and don't need to) be configured with constraints in the constraints file. They are managed through the IP configuration of the "ZYNQ7 Processing System" IP. It is there that you define the connections to the on-board peripherals and select voltage levels etc.

[redpitaya_htw]

Thanks for your answer.

I've already tried to manage the connection in IP configuration.

I've set the eth0 to EMIO. After that, the IP block had the GMII interface as ports....

--> right mouse click : make external port
--> create hdl wrapper
--> copy the new ports out of the wrapper into the components in the top level
--> create matching ports in my main entity and do the port mapping
--> connecting the clocks
--> generate a test signal for the gmii_tx with std_logic_vector
--> generating a bitstream leads to a critical warning which says that their are no physical pins mapped for gmii_tx...

[Nils Roos]

As I said, I suspect that the MIO pins can't be accessed from the PL.

Why do you want to route the mdio signals through the PL ? If you are using the eth0 controller, what is the point of not using the direct connection ?

[redpitaya_htw]

the zynq 7000 manual mentioned that it is possible to map the eth0 to emio. and emio ports should be connectes to the pl.

my plan is to connect two red pitayas via sma cables and just route an ethernet signal from the ethernet phy trough one red pitaya to another and out of the other ethernet phy. thos should happenwithout the usage of mac...

[Nils Roos]

the zynq 7000 manual mentioned that it is possible to map the eth0 to emio. and emio ports should be connectes to the pl.

Mapping the internal peripherals over EMIO into the PL is primarily a way to connect them to user-defined pins in case all MIO pins are occupied.

Connecting to the MIO pins from the PL is not possible (found a thread where Xilinx employees confirm this).

You can eg. activate the second ethernet controller, map it to EMIO and then connect it to the GPIOs on E2 in the PL.
But you can't connect anything in the PL to the existing PHY on the Red Pitaya, because that is hardwired to the MIO pins, which are only available to the PS.

my plan is to connect two red pitayas via sma cables and just route an ethernet signal from the ethernet phy trough one red pitaya to another and out of the other ethernet phy. thos should happenwithout the usage of mac...

Maybe I still don't understand your objective, but why not just put the LAN cable into the first RP ?
If you are planning to "combine" two MDIO busses into one PHY chip, I think that is not possible.

[redpitaya_htw]

http://www.xilinx.com/support/documenta ... 00-TRM.pdf <--- page 527 and following

This chapter says that it should be possible to do.
I've attached a little "paint artwork" for you. maybe this makes my intention a little bit clearer to you.


\\edit: Red Pit. 1 should receive ethernet signals trough a RJ45 cable and send them bitwise with a proprietary protocol via the dac to Red Pit. 2.
Red Pit. 2 should now receive the bitstream over his adc and collect the bitstream until a hole ethernet frame is received.
Now the Red Pit. 2 should reassamble the ethernet frame and send it out trough his Ethernet PHY tp PC2.
This should also work with DAC2 and ADC2 the other way to ensure FULL Duplex Mode.

[Nils Roos]

Thanks, now I understand what you want to do and why you'd like to connect the PHY to the PL. Unfortunately, after reading the relevant documentation I still think it is not possible to do it the way you plan to.

This chapter says that it should be possible to do.

The chapter says that it is possible to connect a GMII interface to the MAC via EMIO, or add support for other interface standards to the MAC in the PL that way.
Take a look at figure 16-7. This is how the Red Pitaya connects to the external PHY device. Notice how the external pins are directly connected to the "MIO Multiplexer" and from there to the "Ethernet Controller". The PL has no connection to the MIO multiplexer. You can route the signals of the ethernet controllers to EMIO, but you can't route the signals of the MIO multiplexer to the PL.

The consequence is that only the integrated MAC can connect to the external Lantiq PHY; the PL can't.
To realize your proprietary MAC-free PHY-to-PHY bridge, you'd have to connect a separate PHY to pins that are accessible to the PL. I don't see any other way.

[redpitaya_htw]

Maybe your right and the best option would it be to use external PHY instead of the given Lantiq but i thought it would be possible to communicate with the MIO MUX through EMIO as Figure 1 on page 6 in "http://www.xilinx.com/support/documenta ... erview.pdf" shows.