How to delay one input by 0.4us?

Placement, modules, components and accessories; the ones that exist and the the nice-to-be's
Post Reply
ronyang@RP
Posts: 7
Joined: Fri Dec 25, 2015 3:10 am

How to delay one input by 0.4us?

Post by ronyang@RP » Mon Aug 29, 2016 11:33 pm

Hi There:

I would like to delay one A/D input (adc_b) by 0.4 us. As far as I know, I could use adc_clk_in as the master clock and design 50 clocks shift register.
However, I have tried both the RAM-based shift register by Xilinx and my own version of shift register, none of them works.

To be more detailed, I change
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
to
assign adc_b_reg = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
ram-based_shift_register delayb (
.D(adc_b_reg), // input wire [13 : 0] D
.CLK(adc_clk_in), // input wire CLK
.Q(adc_b) // output wire [13: 0] Q
);
with this IP setting:
Image

Or, just use a very stupid way
always @(posedge adc_clk)
begin
inputb_reg[0] <= adc_b_reg;
for(i=1;i<49;i=i+1)
inputb_reg <= inputb_reg[i-1];
end
assign adc_b = inputb_reg[49];

Unfortunately, the signal is not delayed at all...Can someone help me on this?

ronyang@RP
Posts: 7
Joined: Fri Dec 25, 2015 3:10 am

Re: How to delay one input by 0.4us?

Post by ronyang@RP » Mon Aug 29, 2016 11:35 pm

Sorry that in the IP settings, the port width should be 14 instead of 13. No improvements by fixing that.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: How to delay one input by 0.4us?

Post by Nils Roos » Tue Aug 30, 2016 9:14 pm

How do you verify that there is no delay?
I ask because if you use one of the web-apps, it may be that your modified bitstream gets overwritten when the app is started.

Otherwise, your delay seems to be in the right place - though you should use adc_clk instead of adc_clk_in for the IP approach.

ronyang@RP
Posts: 7
Joined: Fri Dec 25, 2015 3:10 am

Re: How to delay one input by 0.4us?

Post by ronyang@RP » Tue Aug 30, 2016 9:47 pm

Nils Roos wrote:How do you verify that there is no delay?
I ask because if you use one of the web-apps, it may be that your modified bitstream gets overwritten when the app is started.

Otherwise, your delay seems to be in the right place - though you should use adc_clk instead of adc_clk_in for the IP approach.
Hi Nils:

Thanks for the reply!
I just replace the fpga_0.93.bit in /opt/redpitaya/fpga and use the web program.
Now the IP shift register works by using adc_clk. But the for-loop one still won't work. Anyway., thanks for that and if you have any other suggestion on the for-loop one, I am glad to know.

Best,
Ron

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: How to delay one input by 0.4us?

Post by Nils Roos » Tue Aug 30, 2016 9:54 pm

I have one comment on the for loop: the condition should be "i<=49", otherwise there will be no input to adc_b .

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 22 guests