How to delay one input by 0.4us?
Posted: Mon Aug 29, 2016 11:33 pm
Hi There:
I would like to delay one A/D input (adc_b) by 0.4 us. As far as I know, I could use adc_clk_in as the master clock and design 50 clocks shift register.
However, I have tried both the RAM-based shift register by Xilinx and my own version of shift register, none of them works.
To be more detailed, I change
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
to
assign adc_b_reg = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
ram-based_shift_register delayb (
.D(adc_b_reg), // input wire [13 : 0] D
.CLK(adc_clk_in), // input wire CLK
.Q(adc_b) // output wire [13: 0] Q
);
with this IP setting:
Or, just use a very stupid way
always @(posedge adc_clk)
begin
inputb_reg[0] <= adc_b_reg;
for(i=1;i<49;i=i+1)
inputb_reg <= inputb_reg[i-1];
end
assign adc_b = inputb_reg[49];
Unfortunately, the signal is not delayed at all...Can someone help me on this?
I would like to delay one A/D input (adc_b) by 0.4 us. As far as I know, I could use adc_clk_in as the master clock and design 50 clocks shift register.
However, I have tried both the RAM-based shift register by Xilinx and my own version of shift register, none of them works.
To be more detailed, I change
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
to
assign adc_b_reg = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
ram-based_shift_register delayb (
.D(adc_b_reg), // input wire [13 : 0] D
.CLK(adc_clk_in), // input wire CLK
.Q(adc_b) // output wire [13: 0] Q
);
with this IP setting:
Or, just use a very stupid way
always @(posedge adc_clk)
begin
inputb_reg[0] <= adc_b_reg;
for(i=1;i<49;i=i+1)
inputb_reg <= inputb_reg[i-1];
end
assign adc_b = inputb_reg[49];
Unfortunately, the signal is not delayed at all...Can someone help me on this?