Redpitaya Forum

I struggled to understand whether the “low noise” improvement to 125-14 always had been a part of 122-16 already?

I want to opt for 7020 FPGA (both), use it in 14 or 16bits, couple it to 50 ohms (ad- on needed for 125-14) and want to run it both on external and internal clock (not sure).

And is low noise improvement for input only? Or also output?

I want to use it for wideband (OFDM) processing (reception) of whole HF spectrum.

Hello ph2thet,

The 125-14 low-noise version has better analog power regulators and the improvements suggested here:
https://ln1985blog.wordpress.com/2016/0 ... rformance/
The effects should be noticeable on both inputs and outputs.

SDRlab 122-16 is out-of-the-box meant as a "low-noise" version, but is designed a bit differently (50 Ohm inputs and no analog filters behind them).

As for the choice between the 125-14 and 122-16, I will leave it up to you.

In any case, I would suggest checking out Pavel Demin's Alpine version of the OS:
https://github.com/pavel-demin/red-pitaya-notes

Thank you!

Read the concerns and understand them (a bit). This was 2016. Have these modifications been equally applied to low noise 125-14 as to 122-16? That wasn’t clear to me.

Your statement about 122-16 having 50Ohm impedance I understand. No amplification. But to the point of high input impedance of 125-15, is there a variable gain amplifier in 125-14 that I can find schematic of?

Your statement about no filtering on 122-16 I did not understand. Is there no anti aliasing filter at half of 122MHz?

I will only be working on 1.8MHz to 30MHz hence making it a radio application. But not at a subset of that spectrum (IF) as most SDR use cases will apply to. No digital down conversion. I will be processing 1200 sub carriers in parallel (relative simple operations luckily). So no tuning. Giving this background since I am looking for your input on what model to use. My requirements are:
* -1V to 1V signal
* AC coupled
* 1.8 to 30MHz only
* sample rate 75Mhz
* external ADC clock optional
* HF bandpass filter (external)

Thanks for the update.

The modifications described in the article were applied to the STEMlab 125-14, together with better analog power regulators and other improvements, to create the STEMlab 125-14 low-noise version.

The 122-16 was designed with these changes in mind. Here is a link to the specifications and the development schematics:
https://redpitaya.readthedocs.io/en/lat ... 6/top.html
(you can go up to 500 MHz with undersampling)

Thank you. My confusion is growing by your link provided. It contains the specs and schematic of 122-16 SDR. Differences:
Spec: RF input impedance: 50 Ohm, schematic: 1M Ohm
Spec: voltage: .5Vpp, schematic: -1V to +1V

Do you understand my confusion?

There is a mistake in the schematics, thank you for pointing it out.

The correct input impedance and other parameters are in the documentation table (so 0.5 Vpp input voltage and 50 Ohm input impedance)
The schematics will be updated.

Also, there is no low-pass filter on the fast analog inputs for the SDRlab.

Ok, thank you.

Could you send me the correct schematic? This was quite confusing so far and I am trying to create a wideband radio with either the 14 or 16 but one. Knowing the in/output topology is crucial.

Could you also point me to the schematic of the 125-14LN?

Another question I have is on the external clock circuit. Is that really tied to ground via 0R0 resistors as per the schematic? Sampling at 122MHz requires a pure clock signal I have attached your schematic and a typical schematic of a 125MSPS Analog Devices ADC. I need the latter filtering. Preferably close to the ADC. But when it is shorted to ground my options are gone. Could you let me know? Both for the LN as the SDR type?

Thanks!

Ps: I cannot upload 250kB screenshots. Please refer to the schematic you provide for absence of clock filter circuit that is tied to GND. And for datasheet of your ADC’s development kit for a reference design.

Second try to upload the two screenshots. The forum software will not allow it (too large at 250kB)

Hello ph2thet,

Thank you for the update.

The schematic links that I have shared so far are the correct ones. Please just ignore the input impedance and input voltage note for the SDRlab (just the note needs to be changed).

Here is the link where you can find all schematics (STEMlab 125-14 low-noise is labeled as STEMlab 125-14 LN):
https://redpitaya.readthedocs.io/en/lat ... l#hardware

Direct link to STEMlab 125-14 Z7020 Version schematics:
https://redpitaya.readthedocs.io/en/lat ... schematics

Please note that the schematics are development schematics (Red Pitaya is not fully hardware open-source). The schematics for SDRlab and External clock SDRlab in the documentation are the same (and represent the SDRlab 122-16 schematic (internal clock)). You can find the modifications for the external clock here (the External clock uses ADC CLK+ and ADC CLK- pins which are NOT tied to the ground):
https://redpitaya.readthedocs.io/en/lat ... -adc-clock


Correct me if I am wrong, but you are looking for an external clock version of the board with Zynq 7020, are you not?


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Please send the images either as links or to support@redpitaya.com (mentioning your forum name ph2thet in the mail).