Bus speed FPGA core - DDR3 Ram

Placement, modules, components and accessories; the ones that exist and the the nice-to-be's
bhaskarm
Posts: 6
Joined: Sat Jul 16, 2016 6:48 pm

Re: Bus speed FPGA core - DDR3 Ram

Post by bhaskarm » Tue Aug 16, 2016 9:31 pm

Hello Nils,
Thanks for the information. I can see that the v0.96 release has added AXI4 bus and DMA to the external buffer. I can use the v0.96 pre-release code in my design as long as it is marginally stable. Who will be the right person with more information about the v0.96 release?

Regards,
Bhaskar.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Bus speed FPGA core - DDR3 Ram

Post by Nils Roos » Sat Aug 20, 2016 11:10 pm

You could try contacting forum user izi. He is the FPGA developer at Red PItaya.

bhaskarm
Posts: 6
Joined: Sat Jul 16, 2016 6:48 pm

Re: Bus speed FPGA core - DDR3 Ram

Post by bhaskarm » Mon Aug 22, 2016 7:17 pm

Thanks for the help Nils. I checked out the v0.96 code and it seems that the DAC stream handling is still under development. The signal generator block still has an internal BRAM to store samples for the DAC.
I will contact izi for futher help.

Bhaskar.

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