Slow DAC resolution

Placement, modules, components and accessories; the ones that exist and the the nice-to-be's
Post Reply
ttemsk
Posts: 10
Joined: Sun Jul 19, 2015 8:04 pm

Slow DAC resolution

Post by ttemsk » Sun Jul 19, 2015 8:58 pm

Colleaques,

I notice that slow DAC voltage can only be adjusted in 12mV steps, which would imply only ~7bit resolution within the 1.8V full range, not the specified 12 bits. I'm using the "monitor -sdac" command to set the voltages. The resulting voltage is easiest to verify with the "monitor -ams" command, but use of an external DVM also indicates 12mV steps. I'm using the ecosystem v0.93-14, although I first observed this with the ecosystem v0.92-378.

What gives? There was some discussion about the PWM technique the R.P. uses in tinyurl.com/njjojpw , which appears a bit similar to tinyurl.com/lzbshov .

Regards,
Mikko Kiviranta

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Slow DAC resolution

Post by Nils Roos » Mon Jul 20, 2015 12:36 am

Hi,
what you describe has its cause in the "monitor -sdac" implementation. The slow DAC works as described in the links you posted and at the advertised resolution, only the monitor utility does not fully use it - because getting the additional 4 bits is a bit of an awkward computation, presumably.

To use the full resolution with the monitor tool, you could write the data to the DAC registers (0x40400020, .., 0x4040002c) directly. Here's an explanation how to calculate sample data.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Slow DAC resolution

Post by Nils Roos » Mon Jul 20, 2015 1:01 am

I just tried to put the description into a bit of code, and it's not even as unwieldy as I'd have thought it would be:

Code: Select all

int sample(double voltage) {
  int n;
  if (voltage > 1.8) voltage = 1.8;
  if (voltage < 0) voltage = 0;
  n = (voltage / 1.8) * 2496.;
  return ((n / 16) << 16) + (0xffff >> (16 - (n % 16)));
}

irain04
Posts: 12
Joined: Wed Jul 22, 2015 1:33 pm

Re: Slow DAC resolution

Post by irain04 » Thu Jul 23, 2015 12:16 pm

Hi Nils Roos,

Sorry Mikko Kiviranta for using your thread to ask Roos about my issue but it's also about DAC so I think I should better ask here.

I want to control fast DAC by using FPGA. Do you have any documents for this?
I don't know how FPGA and fast DAC are connected together, can you teach me?

Thank you all.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Slow DAC resolution

Post by Nils Roos » Thu Jul 23, 2015 7:16 pm

Hi,
irain04 wrote:but it's also about DAC so I think I should better ask here
Well, this thread is about the other DAC, but I guess a brief digression wont hurt.

This code in red_pitaya_top.v feeds data to the fast DAC:

Code: Select all

wire  [ 15-1: 0] dac_a_sum       ;
wire  [ 15-1: 0] dac_b_sum       ;

assign dac_a_sum = $signed(asg_a) + $signed(pid_a);
assign dac_b_sum = $signed(asg_b) + $signed(pid_b);
Assign your own signal to dac_a_sum/dac_b_sum, and you have full control over the fast DAC.

irain04
Posts: 12
Joined: Wed Jul 22, 2015 1:33 pm

Re: Slow DAC resolution

Post by irain04 » Sat Jul 25, 2015 7:43 am

Thanks a lot, Nils Roos.

ttemsk
Posts: 10
Joined: Sun Jul 19, 2015 8:04 pm

Re: Slow DAC resolution

Post by ttemsk » Sun Sep 13, 2015 10:45 am

Nils Roos wrote:I just tried to put the description into a bit of code, and it's not even as unwieldy as I'd have thought it would be:
...
Thanks a lot for the reply. I was in the process of trying something similar with the LUA compiler (provided with the RP infrastucture), but got stuck on a Zmodem problem, which I just submitted.

ttemsk
Posts: 10
Joined: Sun Jul 19, 2015 8:04 pm

Re: Slow DAC resolution

Post by ttemsk » Mon Mar 27, 2017 5:03 pm

I just wanted to check whether the slow DAC resolution problem has gotten fixed natively in the new Ecosystem version. But I notice that the 'monitor' command line utility does not work at all in the 0.97-336 ecosystem. For instance, the command 'monitor -sdac 0.5 0.6 0.7 0.8' has no effect on voltages of of the AO0 ... AO3 pins.

The option -ams does not seem to be available in the 'monitor' at all.

The 'generate' command line utility does not seem to work either, it has no effect on the fast DAC outputs. The generate version is 0.97-336-4506f6e-4506f6e, same for the 'monitor'.

Do others observe similar behaviour, or am I missing something?

Regards,
Mikko

ttemsk
Posts: 10
Joined: Sun Jul 19, 2015 8:04 pm

Re: Slow DAC resolution

Post by ttemsk » Mon Mar 27, 2017 5:25 pm

OK, I notice the special FPGA image was required:

Code: Select all

cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg
The 'generate' utility seems to work now. The 'monitor' utility still has no effect on slow DAC outputs, but the bundled 'monitor_old' seems to work, albeit still with the 12 mV resolution. Ok, need to implement the bit pattern trick, Bresenham's algorithm would simplify matters.

Regards,
Mikko

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 26 guests