Redpitaya Forum

Nils Roos wrote:Hi,

I recommend you either fork / clone the RedPitaya github repository or download the contents as a zip archive. Within that, the folder "fpga" has all code that is used to build the fpga logic.
But ... with the 0.94 ecosystem release, a proper project file for the Vivado GUI is no longer included. This means you'll have to do some preparations to work with the project in Vivado. Nothing too complicated though, just do the following:

1. edit the file fpga/red_pitaya_vivado_project.tcl and change the line

   Code: Select all

   read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v

   into

   Code: Select all

   read_verilog project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v

2. start Vivado, at the bottom of the main screen you have the "Tcl Console"
3. use the tcl console to navigate into the fpga-folder with the command "cd" (on my machine it would be "cd /Users/Nils/Documents/RedPitaya/fpga")
4. execute "source red_pitaya_vivado_project.tcl" in the tcl console and watch while Vivado magically builds the project

After all this has finished, you have a new folder "project" in the fpga-folder which contains the projectfile and all sources.

read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v