Trying to use SDK

[enllobu]

IT WORKS!!! Thank you a lot Nils!!

[Nils Roos]

Well, that was quick !

Glad I could help.

[benpaodexiniu]

Hi everyone, I want to custom my own axi ip to communicate with arm, but I have read many information about how to create and pankage axi ip and am still confused it.Can anybody teach me how to custom axi ip detailed?

[benpaodexiniu]

Hi Nils, I want to custom my own axi ip to communicate with arm, but I have read many information about how to create and pankage axi ip and am still confused it. Can you teach me how to custom axi ip detailed?

[Nils Roos]

Hi,
I have not yet needed to create a customized ip design, so I can only tell you some general principles.
For a design with a simple control interface to the ARM cores, you need the following:

• an AXI slave interface in your design - include an IP that has one, or code your own
• a free AXI master interface on the processing_system_7 IP - for example one of the AXI GP masters
• an entry in the Address Map that tells the processing system where to map your IP into the bus address space
• a connection between your AXI slave and the ZYNQ's AXI master

Once you have all these things set up and connected, the ARM cores can address your IP by way of the mapped address region.

This tutorial gives a good overview of the procedures to create such a design. Once you have your IP tested and ready, you package it (without the processing_system7), following this tutorial.

[benpaodexiniu]

Hi Nils, Thanks a lot for your quick response.I am new to FPGA and ARM and sorry to ask some naive question. I have understand how to custom own ip but not very familiar. I have downloaded the redpitaya fpga verilog code and where to find the whole block design(I mean the ip customed by the original code)?

[Nils Roos]

The block design is created on-the-fly during the build process. See this topic for instructions how you can work with the block design (with customized IP).

[benpaodexiniu]

Hi Nils, In RedPitaya_HDL_memory_map, the Arbitrary signal generator's address range is 0x40200000~0x402FFFFF. But why I didn't see the Arbitrary signal generator's address range in address editor of vivado?

[Nils Roos]

But why I didn't see the Arbitrary signal generator's address range in address editor of vivado?

In the address editor, the M_AXI_GP0 entry covers 0x40000000 - 0x7fffffff. This includes the ASG's range of 0x40200000 - 0x402fffff. That means that

1. accesses to the ASG's address range are routed to the M_AXI_GP0 bus (see right-hand side of system.bd diagram)
2. the bus is connected through the system_wrapper.v to the red_pitaya_ps.v signals "gp0_maxi_..."
3. "gp0_maxi_..." is converted by module axi_slave_gp0 (axi_slave.v) into "sys_..."
4. "sys_..." becomes "ps_sys_..." in red_pitaya_top.v, where it is decoded into blocks of 0x00100000 . The third of those blocks is the ASG.

[benpaodexiniu]

Hi Nils, I always thought the ASG moudle had been customed a AXI IP.Thanks a lot for your detailed answer.And there are other questions:
(1) If i want to develop my own linux application with FPGA design, can i develop it just in windows enviroment and how about sdk?
(2) I want to write device tree file for my FPGA design but when I type make command in linux and failed with a info (a valid license not found ) so I can't get the device tree source code. My question is that there is another way to get device tree source code in windows?