Anti-aliasing inside FPGA?

Applications, development tools, FPGA, C, WEB
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Tomaok
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Joined: Thu Jun 16, 2016 9:58 am

Anti-aliasing inside FPGA?

Post by Tomaok » Thu Jan 26, 2017 2:22 pm

Hello everybody,

Is there a way to make an anti-aliasing filter inside the FPGA?
thanks for any comments/suggestions

TOM

Nils Roos
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Location: Königswinter

Re: Anti-aliasing inside FPGA?

Post by Nils Roos » Sat Jan 28, 2017 4:13 pm

Digital anti-aliazing filters work with an oversampled signal. If the (fixed) sampling rate of 125MSps is sufficiently oversampled for your desired target bandwidth, then the answer is yes.

You can implement a digital filter in the FPGA that reduces the bandwidth of the sampled signal (62.5MHz) to your target bandwidth (x), and then apply decimation to reduce the oversampled rate to the rate you actually need. This avoids aliazing effects of signal energy in the band from x to 62.5MHz that you would get by just decimating.

Of course, this is constrained by the available computing resources of the FPGA.
All in a day's work for Bicycle Repair Man

Tomaok
Posts: 5
Joined: Thu Jun 16, 2016 9:58 am

Re: Anti-aliasing inside FPGA?

Post by Tomaok » Sun Jan 29, 2017 6:58 pm

thank you Nils for your answer, this is exactly what i would like to do.
But unfortunately i don't know how to make such filter inside a FPGA( for now i only know how to work on uP side ).

Could you point me to some examples that show how to modify the actual FPGA bit file?

As you said, this is constrained by the available computing resources of the FPGA,
So the question is does the FPGA as enough resources to do this?
Or should i remove many functionalities to have enough resources?

thanks for any comments/suggestions

TOM

Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Anti-aliasing inside FPGA?

Post by Nils Roos » Mon Jan 30, 2017 1:10 am

Could you point me to some examples that show how to modify the actual FPGA bit file?
You modify the bitfile by changing things in the Verilog code or block design and then rebuilding it.
Here is an example for adding a filter module in the Verilog code. For block designs, I believe there is a filter wizard in Vivado.
So the question is does the FPGA as enough resources to do this?
That depends on the complexity of your filter. I have no practical experience in designing digital (or analog) filters, so I can't give an estimate.
All in a day's work for Bicycle Repair Man

hunterakins
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Joined: Thu Apr 06, 2017 9:31 pm
Location: Berkeley, CA

Re: Anti-aliasing inside FPGA?

Post by hunterakins » Mon Sep 11, 2017 11:33 pm

Are you sure it doesn't have this feature already?
I fed a 16kHz 1Vpp signal into the Red Pitaya. At sampling rate of 122 kHz it showed up fine.
At a sampling rate of 15.258kHz I would expect a 1Vpp aliased signal at .742 kHz, but instead I got a .04Vpp aliased signal at .742kHz.
This also happens if you use the oscilloscope app and change the time scale.

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