Applications, development tools, FPGA, C, WEB
#7929 by downunderthunder123
Thu Sep 07, 2017 1:50 pm
Hi,
since a while I am struggling with the fpga vivado projects that are good to get familiar with fpga on the red pitaya.
For instance I got the
stop watch running --> http://antonpotocnik.com/?p=489265
the LED and knight rider projects worked for me, too...... I already did some minor adaptions on the projects in order to understand better.

the project no. 4 is a frequency counter that I managed to output a bitstream.... but still with some strange behaviour.... (I don't care so much).

Based upon the the stop watch project what changes do I have to do in order to just get data from IN1 to OUT1?
that I guess would be a good starting point for doing some signal processing later on............

Best Regards

Oliver
#7961 by irain04
Mon Sep 18, 2017 3:54 am
Hi Oliver,

For the IN1:
You can find the following code lines in https://github.com/RedPitaya/RedPitaya/blob/master/fpga/prj/v0.94/rtl/red_pitaya_top.sv:

Code: Select all////////////////////////////////////////////////////////////////////////////////
// ADC IO
////////////////////////////////////////////////////////////////////////////////

// generating ADC clock is disabled
assign adc_clk_o = 2'b10;
//ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
//ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));

// ADC clock duty cycle stabilizer is enabled
assign adc_cdcs_o = 1'b1 ;

logic [2-1:0] [14-1:0] adc_dat_raw;

// IO block registers should be used here
// lowest 2 bits reserved for 16bit ADC
always @(posedge adc_clk)
begin
  adc_dat_raw[0] <= adc_dat_i[0][16-1:2];
  adc_dat_raw[1] <= adc_dat_i[1][16-1:2];
end
   
// transform into 2's complement (negative slope)
assign adc_dat[0] = digital_loop ? dac_a : {adc_dat_raw[0][14-1], ~adc_dat_raw[0][14-2:0]};
assign adc_dat[1] = digital_loop ? dac_b : {adc_dat_raw[1][14-1], ~adc_dat_raw[1][14-2:0]};


adc_dat_raw is the raw data from ADC of Red Pitaya, adc_dat[0] is the data of IN1 that you can use as input for signal processing.

For OUT1:
You can find the following code lines in https://github.com/RedPitaya/RedPitaya/blob/master/fpga/prj/v0.94/rtl/red_pitaya_top.sv:
Code: Select all////////////////////////////////////////////////////////////////////////////////
// DAC IO
////////////////////////////////////////////////////////////////////////////////

// Sumation of ASG and PID signal perform saturation before sending to DAC
assign dac_a_sum = asg_dat[0] + pid_dat[0];
assign dac_b_sum = asg_dat[1] + pid_dat[1];

// saturation
assign dac_a = (^dac_a_sum[15-1:15-2]) ? {dac_a_sum[15-1], {13{~dac_a_sum[15-1]}}} : dac_a_sum[14-1:0];
assign dac_b = (^dac_b_sum[15-1:15-2]) ? {dac_b_sum[15-1], {13{~dac_b_sum[15-1]}}} : dac_b_sum[14-1:0];

// output registers + signed to unsigned (also to negative slope)
always @(posedge dac_clk_1x)
begin
  dac_dat_a <= {dac_a[14-1], ~dac_a[14-2:0]};
  dac_dat_b <= {dac_b[14-1], ~dac_b[14-2:0]};
end


dac_dat_a is the data which is sent to DAC to generate OUT1.
Hope this helps.

Cheers,
Trung

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