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VNA SWR mathematics

Last post by pavel « Mon Sep 03, 2018 8:49 am
Replies: 6
by drdieter » Sun Sep 02, 2018 5:31 pm

6 Replies

1650 Views

Last post by pavel
Mon Sep 03, 2018 8:49 am
how change sampling rate 62.5MS/s

Last post by naser1363 « Mon Sep 03, 2018 7:55 am

by naser1363 » Mon Sep 03, 2018 7:55 am

0 Replies

623 Views

Last post by naser1363
Mon Sep 03, 2018 7:55 am
Failed to lock chroot

Last post by liwenz « Thu Jul 19, 2018 5:09 am

by liwenz » Thu Jul 19, 2018 5:09 am

0 Replies

1057 Views

Last post by liwenz
Thu Jul 19, 2018 5:09 am
Set up Istructions for OpenHPSDR mRX PS

Last post by GregMew « Sun Jul 01, 2018 12:34 pm
Replies: 2
by GregMew » Fri Jun 29, 2018 2:02 pm

2 Replies

1292 Views

Last post by GregMew
Sun Jul 01, 2018 12:34 pm
Generate Pulse with FPGA of the RP

Last post by likun « Thu Jun 28, 2018 3:40 pm

by likun » Thu Jun 28, 2018 3:40 pm

0 Replies

683 Views

Last post by likun
Thu Jun 28, 2018 3:40 pm
Where is the OS directory?

Last post by hutzlerlab « Thu Jun 21, 2018 7:44 pm

by hutzlerlab » Thu Jun 21, 2018 7:44 pm

0 Replies

780 Views

Last post by hutzlerlab
Thu Jun 21, 2018 7:44 pm
Switch off / reduce clockspeed of core

Last post by JoWo1994 « Sat Jun 16, 2018 4:37 pm
Replies: 6
by JoWo1994 » Wed Jun 13, 2018 5:29 pm

6 Replies

2126 Views

Last post by JoWo1994
Sat Jun 16, 2018 4:37 pm
Break FPGA because of bad programming

Last post by dbs_jd « Tue Jun 12, 2018 6:31 am

by dbs_jd » Tue Jun 12, 2018 6:31 am

0 Replies

877 Views

Last post by dbs_jd
Tue Jun 12, 2018 6:31 am
data structure via scpi

Last post by aschuetz « Mon Jun 11, 2018 9:40 am

by aschuetz » Mon Jun 11, 2018 9:40 am

0 Replies

666 Views

Last post by aschuetz
Mon Jun 11, 2018 9:40 am
VNA LOAD-Key

Last post by drdieter « Fri Jun 08, 2018 10:51 am
Replies: 2
by drdieter » Thu Jun 07, 2018 7:28 pm

2 Replies

1139 Views

Last post by drdieter
Fri Jun 08, 2018 10:51 am
Adapt ongoing signal

Last post by str « Thu Jun 07, 2018 11:22 am

by str » Thu Jun 07, 2018 11:22 am

0 Replies

698 Views

Last post by str
Thu Jun 07, 2018 11:22 am
Using DMA IP blocks in logic_orig

Last post by kokowang « Tue Jun 05, 2018 6:58 am

by kokowang » Tue Jun 05, 2018 6:58 am

0 Replies

648 Views

Last post by kokowang
Tue Jun 05, 2018 6:58 am
Talking to external DSP via the RP SPI1 (slave mode) on FPGA level?

Last post by pyzahl « Tue May 29, 2018 5:31 am

by pyzahl » Tue May 29, 2018 5:31 am

0 Replies

661 Views

Last post by pyzahl
Tue May 29, 2018 5:31 am
mmap register access in C

Last post by skywalker « Tue May 22, 2018 11:51 am
Replies: 2
by skywalker » Wed May 16, 2018 1:15 pm

2 Replies

1148 Views

Last post by skywalker
Tue May 22, 2018 11:51 am
CW Skimmer problem after software upgrade?

Last post by pavel « Sat May 19, 2018 9:38 pm
Replies: 1
by NY3A » Sat May 19, 2018 8:06 pm

1 Replies

923 Views

Last post by pavel
Sat May 19, 2018 9:38 pm
Modify Spectrum analyzer in C

Last post by robz « Thu May 17, 2018 10:23 am

by robz » Thu May 17, 2018 10:23 am

0 Replies

740 Views

Last post by robz
Thu May 17, 2018 10:23 am
Trouble with Ethernet connection

Last post by amike88 « Tue May 15, 2018 12:56 pm
Replies: 1
by n4zr » Tue May 15, 2018 12:40 pm

1 Replies

777 Views

Last post by amike88
Tue May 15, 2018 12:56 pm
gnuradio and RP digital IO ?

Last post by tech62 « Mon May 14, 2018 11:04 am

by tech62 » Mon May 14, 2018 11:04 am

0 Replies

607 Views

Last post by tech62
Mon May 14, 2018 11:04 am
gnuradio & XADC

Last post by tech62 « Mon May 14, 2018 10:59 am
Replies: 10
by tech62 » Mon Mar 05, 2018 1:23 pm
1

2
10 Replies

2808 Views

Last post by tech62
Mon May 14, 2018 10:59 am
Reading Digital IO

Last post by amike88 « Thu May 10, 2018 6:22 am
Replies: 1
by peterbrad » Thu May 10, 2018 1:27 am

1 Replies

960 Views

Last post by amike88
Thu May 10, 2018 6:22 am
Zynq from Scratch: Boot

Last post by Abinaya « Wed May 09, 2018 8:19 am
Replies: 3
by noah » Wed Jul 08, 2015 5:29 pm

3 Replies

3683 Views

Last post by Abinaya
Wed May 09, 2018 8:19 am
Exporting data from bode plotter

Last post by Arthur Gerrard « Tue May 08, 2018 2:56 pm
Replies: 5
by jialunluo » Thu Nov 10, 2016 8:53 pm

5 Replies

5437 Views

Last post by Arthur Gerrard
Tue May 08, 2018 2:56 pm
how to set host name ip and port for debug in SDK xilinx for redpitaya

Last post by jmadsenee « Mon May 07, 2018 6:14 pm
Replies: 1
by likun » Wed Apr 25, 2018 12:38 pm

1 Replies

916 Views

Last post by jmadsenee
Mon May 07, 2018 6:14 pm
configure the .bit in Vivado

Last post by jmadsenee « Mon May 07, 2018 6:09 pm
Replies: 1
by juanperengüez » Wed May 02, 2018 11:12 pm

1 Replies

763 Views

Last post by jmadsenee
Mon May 07, 2018 6:09 pm
increase work frequency

Last post by jmadsenee « Mon May 07, 2018 4:44 pm
Replies: 1
by juanperengüez » Wed May 02, 2018 12:41 am

1 Replies

844 Views

Last post by jmadsenee
Mon May 07, 2018 4:44 pm

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