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Data not being processed by custom Verilog filtering module?

Last post by sslerose « Thu Jun 08, 2023 9:23 pm

by sslerose » Thu Jun 08, 2023 9:23 pm

0 Replies

4 Views

Last post by sslerose
Thu Jun 08, 2023 9:23 pm
lower voltage at rf output than expected

Last post by nyagaka « Thu Jun 08, 2023 7:55 pm
Replies: 4
by nyagaka » Wed Jun 07, 2023 5:38 pm

4 Replies

53 Views

Last post by nyagaka
Thu Jun 08, 2023 7:55 pm
FPGA programming to sum two fast signals

Last post by Illia « Thu Jun 08, 2023 10:29 am
Replies: 19
by migibagar » Fri Apr 28, 2023 5:51 pm
1

2
19 Replies

949 Views

Last post by Illia
Thu Jun 08, 2023 10:29 am
Possibility of Self-Contained Signal Filter Testing on 125-14

Last post by sslerose « Wed Jun 07, 2023 7:30 pm
Replies: 2
by sslerose » Mon Jun 05, 2023 4:42 pm

2 Replies

44 Views

Last post by sslerose
Wed Jun 07, 2023 7:30 pm
Fast ADC@125MSPS stored at DDR

Last post by Bulova « Tue Jun 06, 2023 5:11 pm
Replies: 9
by beal » Wed May 10, 2023 1:24 am

9 Replies

292 Views

Last post by Bulova
Tue Jun 06, 2023 5:11 pm
Issues loading .bit file on FPGA

Last post by sslerose « Fri May 19, 2023 5:43 pm
Replies: 4
by sourabh-ch » Wed Mar 22, 2023 3:57 pm

4 Replies

1139 Views

Last post by sslerose
Fri May 19, 2023 5:43 pm
Error when attempting to make project in Ubuntu

Last post by sslerose « Fri May 19, 2023 5:34 pm
Replies: 7
by sslerose » Tue Apr 11, 2023 8:56 pm

7 Replies

891 Views

Last post by sslerose
Fri May 19, 2023 5:34 pm
Bare metal ethernet / lwip

Last post by belotserm « Fri May 05, 2023 10:17 pm
Replies: 2
by sgrad » Fri Oct 21, 2022 7:44 am

2 Replies

1806 Views

Last post by belotserm
Fri May 05, 2023 10:17 pm
Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Last post by juretrn « Thu May 04, 2023 7:56 am
Replies: 5
by sbenjamin » Tue Apr 18, 2023 2:06 pm

5 Replies

1342 Views

Last post by juretrn
Thu May 04, 2023 7:56 am
Get 20% off SDRlab122-16

Last post by redpitaya « Tue Apr 18, 2023 12:43 pm

by redpitaya » Tue Apr 18, 2023 12:43 pm

0 Replies

664 Views

Last post by redpitaya
Tue Apr 18, 2023 12:43 pm
Xilinx XADC core

Last post by juretrn « Fri Apr 14, 2023 1:59 pm
Replies: 2
by ansh » Mon Apr 10, 2023 11:56 pm

2 Replies

768 Views

Last post by juretrn
Fri Apr 14, 2023 1:59 pm
How does the red pitaya implement data acquisition from ADCs

Last post by juretrn « Thu Apr 13, 2023 9:41 am
Replies: 3
by ansh » Tue Apr 11, 2023 9:25 pm

3 Replies

763 Views

Last post by juretrn
Thu Apr 13, 2023 9:41 am
Fast quadrature signal CORDIC

Last post by redpitaya « Wed Apr 12, 2023 2:34 pm
Replies: 1
by ansh » Fri Apr 07, 2023 8:15 pm

1 Replies

778 Views

Last post by redpitaya
Wed Apr 12, 2023 2:34 pm
Using the slow DAC from FPGA

Last post by juretrn « Wed Mar 22, 2023 10:38 am
Replies: 4
by fisp » Fri Dec 16, 2022 3:47 pm

4 Replies

1908 Views

Last post by juretrn
Wed Mar 22, 2023 10:38 am
122-16 SDR Lab board files

Last post by belotserm « Tue Mar 21, 2023 6:52 pm
Replies: 5
by belotserm » Sun Mar 19, 2023 12:28 am

5 Replies

1129 Views

Last post by belotserm
Tue Mar 21, 2023 6:52 pm
Error installing Vitis for Pave Demin's SDR dev environment

Last post by belotserm « Tue Mar 21, 2023 6:31 pm

by belotserm » Tue Mar 21, 2023 6:31 pm

0 Replies

836 Views

Last post by belotserm
Tue Mar 21, 2023 6:31 pm
More GPIO

Last post by hamamaher2020 « Thu Feb 16, 2023 5:23 pm
Replies: 3
by hamamaher2020 » Sun Jan 22, 2023 7:49 pm

3 Replies

1314 Views

Last post by hamamaher2020
Thu Feb 16, 2023 5:23 pm
MIO pin and DDR memory

Last post by hamamaher2020 « Thu Feb 16, 2023 4:16 pm

by hamamaher2020 » Thu Feb 16, 2023 4:16 pm

0 Replies

954 Views

Last post by hamamaher2020
Thu Feb 16, 2023 4:16 pm
Black Friday 2022 is here!

Last post by redpitaya « Wed Nov 23, 2022 9:32 am

by redpitaya » Wed Nov 23, 2022 9:32 am

0 Replies

1348 Views

Last post by redpitaya
Wed Nov 23, 2022 9:32 am
Red Pitaya 125-14: FPGA programming

Last post by juretrn « Fri Nov 18, 2022 8:53 am
Replies: 7
by DrT » Mon Oct 17, 2022 3:01 pm

7 Replies

2395 Views

Last post by juretrn
Fri Nov 18, 2022 8:53 am
Using the Red Pitaya as a pure FPGA

Last post by juretrn « Mon Nov 14, 2022 3:23 pm
Replies: 14
by molinat » Wed Oct 29, 2014 5:31 pm
1

2
14 Replies

15495 Views

Last post by juretrn
Mon Nov 14, 2022 3:23 pm
instructions on Build FPGA

Last post by juretrn « Thu Nov 03, 2022 9:01 am
Replies: 1
by DrT » Wed Nov 02, 2022 4:45 pm

1 Replies

1613 Views

Last post by juretrn
Thu Nov 03, 2022 9:01 am
ADC and DAC Gain Select Pins 250-12

Last post by juretrn « Mon Oct 17, 2022 8:42 am
Replies: 3
by taylor_levaur » Thu Oct 13, 2022 5:57 pm

3 Replies

1732 Views

Last post by juretrn
Mon Oct 17, 2022 8:42 am
Integrating a Custom FPGA Module with PS/AXI bus

Last post by juretrn « Mon Jul 25, 2022 8:35 am
Replies: 5
by coreyb » Fri Jul 15, 2022 4:45 am

5 Replies

2930 Views

Last post by juretrn
Mon Jul 25, 2022 8:35 am
Using External Signal as clock to DDS in Vivado

Last post by ashish_iuac « Wed Jul 20, 2022 8:19 am

by ashish_iuac » Wed Jul 20, 2022 8:19 am

0 Replies

1828 Views

Last post by ashish_iuac
Wed Jul 20, 2022 8:19 am

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